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參數(shù)資料
| 型號： | RM4200AD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 模擬運算功能 |
| 英文描述： | ANALOG MULTIPLIER OR DIVIDER, 4 MHz BAND WIDTH, CDIP8 |
| 封裝： | CERAMIC, DIP-8 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大小： | 188K |
| 代理商： | RM4200AD |
2
RC4200
PRODUCT SPECIFICATION
Functional Description
The RC4200 multiplier is designed to multiply two input
currents (I1 and I2) and to divide by a third input current (I4).
The output is also in the form of a current (I3). A simplied
circuit diagram is shown in the Block Diagram. The nominal
relationship between the three inputs and the output is:
The three input currents must be positive and restricted to a
range of 1
mA to 1 mA. These currents go into the multiplier
chip at op amp summing junctions which are nominally at
zero volts. Therefore, an input voltage can be easily
converted to an input current by a series resistor. Any
number of currents may be summed at the inputs. Depending
on the application, the output current can be converted to a
voltage by an external op amp or used directly. This capa-
bilty of combining input currents and voltages in various
combinations provides great versatility in application.
Inside the multiplier chip, the three op amps make the
collector currents of transistors Q1, Q2 and Q4 equal to their
respective input currents (I1, I2, and I4). These op amps are
designed with current source outputs and are phase-compen-
sated for optimum frequency response as a multiplier. Power
drain of the op amps was minimized to prevent the introduc-
tion of undesired thermal gradients on the chip. The three op
amps operate on a single supply voltage (nominally -15V)
and total quiescent current drain is less than 4 mA. These
special op amps provide signicantly improved performance
in comparison to 741-type op amps.
The actual multiplication is done within the log-antilog
conguration of the Q1-Q4 transistor array. These four
transistors, with associated proprietary circuitry, were
specially designed to precisely implement the relationship.
I
3
I
1I2
I
4
---------
1
()
=
V
BEN
kT
Q
-------In
I
CN
I
SN
---------
2
()
=
Previous multiplier designs have suffered from an additional
undesired linear term in the above equation; the collector
current times the emitter resistance. The ICrE term intro-
duces a parabolic nonlinearity even with matched transistors.
Fairchild Semiconductor has developed a unique and propri-
etary means of inherently compensating for this undesired
ICrE term. Furthermore, this Fairchild Semiconductor devel-
oped circuit technique compensates linearity error over tem-
perature changes. The nonlinearity versus temperature is
signicantly improved over earlier designs.
From equation (2) and by assuming equal transistor junction
temperatures, summing base-to-emitter voltage drops around
the transistor array yields:
This equation reduces to:
The rate of reverse saturation current IS1IS2/IS3IS4, depends
on the transistor matching. In a monolithic multiplier this
matching is easily achieved and the rate is very close to
unity, typically 1.0
±1%. The nal result is the desired
relationship:
The inherent linearity and gain stability combined with low
cost and versatility makes this new circuit ideal for a wide
range of nonlinear functions.
KT
q
-------- In
I
1
I
S1
-------
In
I
2
I
S2
-------
In
I
3
I
S3
------- In
I
4
I
S4
-------
–
=
0
3
()
=
I
1I2
I
3I4
---------
I
S1IS2
I
S3IS4
---------------
4
()
=
I
3
I
1I2
I
4
---------
5
()
=
Pin Assignments
1
2
3
4
I2
VOS2
–VS
I3 (Output)
I1
VOS1
GND
I4
8
7
6
5
65-4200-07
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