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參數(shù)資料
| 型號(hào)： | RM100341WFQMLV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 計(jì)數(shù)移位寄存器 |
| 英文描述： | 100K SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CQFP24 |
| 封裝： | CERQUAD-24 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 190K |
| 代理商： | RM100341WFQMLV |
100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (P
n) and outputs (Qn) for parallel op-
eration, and with serial inputs (D
n) and steering logic for bidi-
rectional shifting. The flip-flops accept input data a setup
time before the positive-going transition of the clock pulse
and their outputs respond a propagation delay after this ris-
ing clock edge.
The circuit operating mode is determined by the Select in-
puts S
0 and S1, which are internally decoded to select either
“parallel entry”, “hold”, “shift left” or “shift right” as described
in the Truth Table. All inputs have 50 k
pull-down resistors.
Features
n 35% power reduction of the 100141
n 2000V ESD protection
n Pin/function compatible with 100141
n Voltage compensated operating range = 4.2V to 5.7V
n Standard Microcircuit
Drawing (SMD) 5962-9459101
Logic Symbol
Pin Names
Description
CP
Clock Input
S
0,S1
Select Inputs
D
0,D7
Serial Inputs
P
0–P7
Parallel Inputs
Q
0–Q7
Data Outputs
DS100315-1
August 1998
100341
Low
Power
8-Bit
Shift
Register
1998 National Semiconductor Corporation
DS100315
www.national.com
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