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參數(shù)資料
| 型號： | RJ80530VY700256 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 5/89頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | RJ80530VY700256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
5
Figures
Figure 1. Clock Control States ..........................................................................................15
Figure 2. PLL RLC Filter....................................................................................................23
Figure 3. VTTPWRGD System-Level Connections...........................................................24
Figure 4. Illustration of V
CC
Static and Transient Tolerances (VID = 1.40V)....................29
Figure 5. Illustration of Deep Sleep V
CC
Static and Transient Tolerances (VID setting
= 1.40V) .............................................................................................................30
Figure 6. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform .............41
Figure 7. Differential BCLK/BCLK# Waveform (Common Mode) .....................................41
Figure 8. BCLK/BCLK# Waveform (Differential Mode).....................................................42
Figure 9. Valid Delay Timings ...........................................................................................42
Figure 10.
Setup and Hold Timings...................................................................................43
Figure 11. Cold/Warm Reset and Configuration Timings..................................................43
Figure 12.
Power-on Sequence and Reset Timings..........................................................44
Figure 13. Power Down Sequencing and Timings (VCC Leading)...................................45
Figure 14.
Power Down Sequencing and Timings (V
CCT
Leading) ....................................46
Figure 15.
Test Timings (Boundary Scan) .........................................................................47
Figure 16.
Test Reset Timings...........................................................................................47
Figure 17.
Quick Start/Deep Sleep Timing (BCLK Stopping Method) ...............................48
Figure 18.
Quick Start/Deep Sleep Timing (DPSLP# Assertion Method)..........................48
Figure 19. Enhanced Intel SpeedStep Technology/Deep Sleep Timing...........................49
Figure 20.
BCLK (Single Ended)/PICCLK Generic Clock Waveform ................................51
Figure 21.
Maximum Acceptable Overshoot/Undershoot Waveform.................................52
Figure 22.
Socketable Micro-FCPGA Package - Top and Bottom Isometric Views ..........56
Figure 23.
Socketable Micro-FCPGA Package - Top and Side View................................57
Figure 24. Socketable Micro-FCPGA Package - Bottom View .........................................58
Figure 25.
Micro-FCBGA Package – Top and Bottom Isometric Views ............................60
Figure 26.
Micro-FCBGA Package – Top and Side Views ................................................61
Figure 27.
Micro-FCBGA Package - Bottom View.............................................................62
Figure 28. Pin/Ball Map - Top View...................................................................................63
Figure 29. PLL Filter Specifications ..................................................................................88
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
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