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| 型號(hào)： | RJ80530VY700256 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 41/89頁(yè) |
| 文件大小： | 1672K |
| 代理商： | RJ80530VY700256 |
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Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
41
Table 29. Enhanced Intel SpeedStep Technology AC Specifications
Symbol
Parameter
Min
Max Unit Figure
Notes
T57
GHI# Setup Time from BCLK Restart or DPSLP#
deassertion
150
ns
19
Note 1
T58
GHI# Hold Time from BCLK Restart or DPSLP#
deassertion
30
μ
s
19
Note 1
T59
GHI# Sample Delay
10
μ
s
ns
19
Note 1
T60
NOTES:
1.
GHI# is ignored until 10
μ
s after BCLK, BCLK# stop or DPSLP# assertion, the setup and hold window must
occur after this time.
2.
BCLK, BCLK# must meet the BCLK AC specification from within 150 ns of turning on (rising above V
IL,BCLK
).
3.
This specification applies to the exit from the Deep Sleep state whether or not an Enhanced Intel SpeedStep
technology operating mode transition occurs.
BCLK Settling Time
150
19
Notes 2, 3
Figure 6. BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform
CLK
V
H
V
L
V
TRIP
T
h
T
l
T
p
T
r
T
f
D0003-01
NOTES
:
T
r
=T5S, T5S1, T34, T25 (Rise Time)
T
f
=T6S, T6S1, T35, T26 (Fall Time)
T
h
=T3S, T3S1, T32, T23 (High Time)
T
l
=T4S, T4S1, T33, T24 (Low Time)
T
p
=T1S, T1S1, T31, T22 (Period)
V
TRIP
=1.25V for BCLK (Single Ended);1.0V for PICCLK; 1.0V for TCK
V
L
CMOSREF
-0.2V) for TCK
V
H
= 2.0V for BCLK (Single Ended);1.6V for PICCLK; (V
CMOSREF
+0.2V) for TCK
Figure 7. Differential BCLK/BCLK# Waveform (Common Mode)
BCLK
BCLK#
Vcross
V2,V3 (max)
V1,V3 (min)
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