參數(shù)資料
型號(hào)： RJ80530VY700256
英文描述： Microprocessor
中文描述： 微處理器
文件頁(yè)數(shù)： 24/89頁(yè)
文件大小： 1672K
代理商： RJ80530VY700256
Mobile Intel
Pentium
III Processor-M Datasheet
24
Datasheet
298340-002
Figure 3. VTTPWRGD System-Level Connections
Voltage Regulator
Processor
Clock Generator
Vcct
Vttpwrgd
(output)
Vttpwrgd
(input)
Vttpwrgd#
(input)
Vcct
10k
Vcct
3.3V
100k
1.2V to 3.3V Level Shifter
1k
3.3
System Bus Clock and Processor Clocking
The BCLK and BCLK# clock inputs directly control the operating speed of the system bus interface.
All system bus timing parameters are specified with respect to the crossing point of the rising edge of
the BCLK input and falling edge of the BCLK# input. The Mobile Intel Pentium
III
Processor-M core
frequency is a multiple of the BCLK frequency. The processor core frequency is configured during
manufacturing. The configured bus ratio is visible to software in the Power-on configuration register.
See Section 7.2 for details.
Multiplying the bus clock frequency is necessary to increase performance while allowing for easier
distribution of signals within the system. Clock multiplication within the processor is provided by the
internal Phase Lock Loop (PLL), which requires constant frequency BCLK, BCLK# inputs. During
Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to acquire the phase
of BCLK and BCLK#. This time is called the PLL lock latency, which is specified in Section 3.7, AC
timing parameters T18 and T47.
3.4
Enhanced Intel SpeedStep Technology
The Mobile Intel Pentium
III
Processor-M supports Enhanced Intel SpeedStep technology, which
enables the processor to operate in two modes, the “Maximum Performance Mode” or the “Battery
Optimized Mode”. Each frequency and voltage pair identifies the operating mode. The voltage
provided to the processor must meet the core voltage specification for the current operating mode. If an
operating mode transition is made, then the system logic must direct the voltage regulator to regulate to
the voltage specification of the other mode. After reset, the processor will start in the lower of its two
core frequencies, so the core voltage must meet the lower voltage specification. Any RESET# assertion
will force the processor to the lower frequency, and the core voltage must behave appropriately. INIT#
assertions ("soft" resets) and APIC bus INIT messages do not change the operating mode of the
processor. Some electrical and thermal specifications are for a specific voltage and frequency. The
Mobile Intel Pentium
III
Processor-M will meet the electrical and thermal specifications specific to the
current operating mode, and it is not guaranteed to meet the electrical and thermal specifications
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