- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372063 > RJ80530VY700256 Microprocessor PDF資料下載
參數(shù)資料
| 型號(hào)： | RJ80530VY700256 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁(yè)數(shù)： | 19/89頁(yè) |
| 文件大?。?/td> | 1672K |
| 代理商： | RJ80530VY700256 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)
Mobile Intel
Pentium
III Processor-M Datasheet
298340-002
Datasheet
19
3.
Electrical Specifications
3.1
Processor System Signals
Table 5
lists the processor system signals by type. All AGTL signals are synchronous with the BCLK
and BCLK# signals. All TAP signals are synchronous with the TCK signal except TRST#. All CMOS
input signals can be applied asynchronously.
Table 5. System Signal Groups
Group Name
Signals
AGTL Input
BPRI#, DEFER#, RESET#, RSP#
AGTL Output
PRDY#
AGTL I/O
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#, REQ[4:0]#,
RP#, RS[2:0]#, TRDY#
1.5V CMOS Input
A20M#, DPSLP#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#,
STPCLK#
1.8V CMOS Input
PWRGOOD
1.5V Open Drain Output
FERR#, IERR#
3.3V Open Drain Output
BSEL[1:0], VID[4:0]
1.25V input
GHI#, VTTPWRGD
Clock
BCLK, BCLK# (Differential Mode)
2.5V Clock Input
BCLK (Single Ended Mode)
APIC Clock
PICCLK
APIC I/O
PICD[1:0]
Thermal Diode
THERMDC, THERMDA
TAP Input
TCK, TDI, TMS, TRST#
TAP Output
TDO
Power/Other
CLKREF, CMOSREF, EDGECTRLP, NC, NCTRL, PLL1, PLL2, RTTIMPEDP, V
CC
,
V
CCT
, V
REF
, V
SS,
NOTES:
1. V
is the power supply for the core logic.
2. PLL1 and PLL2 are power/ground for the PLL analog section. See section 3.2.2 for details.
3. V
CCT
is the power supply for the system bus buffers.
4. V
REF
is the voltage reference for the AGTL input buffers.
5. V
SS
is system ground.
The APIC data and TAP outputs are Open-drain and should be pulled up to 1.5V using resistors with
the values shown in Table 6. If Open-drain drivers are used for input signals, then they should also be
pulled up to the appropriate voltage using resistors with the values shown in Table 6.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RJ80530VZ733256 | Microprocessor |
| RHFL4913 | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| RHFL4913S50-04V | THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS |
| RHFL4913ESY5005V | Converta Box Enclosure; Enclosure Material:Aluminum; External Height:2"; External Width:8"; External Depth:4"; Enclosure Color:Natural |
| RHFL4913ESY3305V | Standard Recovery Rectifier; Forward Current:20A; Forward Current Average:12.7A; Forward Current Avg Rectified, IF(AV):12.7A; Forward Surge Current Max, Ifsm:300A; Forward Voltage:1.1V; Forward Voltage Max, VF:1.1V RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RJ80530VY800256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RJ80530VZ800256 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| RJ80535GC0171M | 制造商:Rochester Electronics LLC 功能描述:MOBILE PENTIUM M,1.4GHZ,1M,UFCBGA - Bulk 制造商:Intel 功能描述: |
| RJ80535GC0171M S L6F5 | 制造商:Intel 功能描述:MPU Pentium? M Processor RISC 32-Bit 130nm 1.4GHz 479-Pin HPBGA Tray 制造商:Intel 功能描述:PENTIUM M PROCESSOR 1.40 GHZ |
| RJ80535GC0211M | 制造商:Intel 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。