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參數(shù)資料
| 型號(hào)： | Q67101-H5173-A701 |
| 廠商： | SIEMENS AG |
| 英文描述： | DDC-PLUS-Deflection Controller |
| 中文描述： | DDC的加偏轉(zhuǎn)控制器 |
| 文件頁(yè)數(shù)： | 24/39頁(yè) |
| 文件大?。?/td> | 199K |
| 代理商： | Q67101-H5173-A701 |
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SDA 9362
Semiconductor Group
24
1998-02-01
b)
Case of STE = 1
In this case the control item Vertical blanking time is an extension for the V-blanking
pulse.
- If BSE = 1 and VBT = 0 the V-blanking pulse has its minimum: it starts always at
end of scan (line B in Fig. below) and ends at start of scan (line C) defined by the
control items
Start Vertical Scan
(if SSE = 1) and
Vertical Scan
.
- BSE = 1 and (128 > VBT > 0) extend the V-blanking pulse according to the
following
relationship
(If VBT > 127 this value is ignored and replaced by VBT - 128):
VBL starts VBT / 2 lines (even field) respectively (VBT + 1) / 2 lines (odd field)
prior to line B.
VBL ends (VBT + 1) / 2 lines (even field) respectively VBT / 2 lines (odd field) after
end of line C.
Possible start points are only the beginning of line.
- If BSE = 0 (after power on) the control item
Vertical Blanking Time
is disabled
and VBL starts 4 lines prior to end of scan (line B) and ends 4 lines after start of scan
(line C).
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