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參數(shù)資料
| 型號(hào)： | Q67101-H5173-A701 |
| 廠商： | SIEMENS AG |
| 英文描述： | DDC-PLUS-Deflection Controller |
| 中文描述： | DDC的加偏轉(zhuǎn)控制器 |
| 文件頁數(shù)： | 12/39頁 |
| 文件大?。?/td> | 199K |
| 代理商： | Q67101-H5173-A701 |
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SDA 9362
Semiconductor Group
12
1998-02-01
2.2
The system clock for the SDA 9362 has to be generated externally (e.g. in the
SDA 9206) and applied to pin CLL. Its frequency must be always the line frequency
(defined by the horizontal time reference HSYNC) multiplied by 864. If no HSYNC signal
is available an internal horizontal synchronisation signal is derived from CLL (CLL
divided by 879).
The input signal at VSYNC is the vertical time reference. It has to pass a window
avoiding too short or long V-periods in the case of distorted or missing VSYNC pulses.
The window allows a VSYNC pulse only after a minimum number of lines from its
predecessor and sets an artificial one after a maximum number of lines. The window size
is programmable by
Ι
2
C Bus.
The beam current dependent input signal IBEAM is A/D converted and then digitally
processed. The A/D Converter requires a clock frequency twice the frequency of CLL
which is generated by an internal analog PLL with an external loop filter at pin LF.
Values which influence shape and amplitude of the output signals are transmitted as
reduced binary values to the SDA 9362 via
Ι
2
C Bus. A CPU which is designed for speed
reasons in a pipe line structure calculates in consideration of feedback signals (e.g.
IBEAM) values which exactly represent the output signals. These values control after
D/A conversion the external deflection and raster correction circuits. The CPU firmware
is stored in an internal ROM.
Circuit Description
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