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    參數(shù)資料
    型號： PSD935G2-70U
    廠商： 意法半導(dǎo)體
    英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers
    中文描述： 在8片位微控制器可配置存儲系統(tǒng)
    文件頁數(shù)： 59/91頁
    文件大小： 488K
    代理商： PSD935G2-70U
    PSD9XX Family
    PSD935G2
    58
    Bit 1 0 = Automatic Power Down (APD) is disabled.
    1 = Automatic Power Down (APD) is enabled.
    Bit 3 0 = PLD Turbo is on.
    1 = PLD Turbo is off, saving power.
    Bit 4 0 = CLKIN input to the PLD AND array is connected.
    Every CLKIN change will power up the PLD when Turbo bit is off.
    1 = CLKIN input to PLD AND array is disconnected, saving power.
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    *
    *
    *
    PLD
    PLD
    Turbo
    *
    APD
    Enable
    *
    Array clk
    1 = off
    1 = off
    1 = on
    Table 26. Power Management Mode Registers (PMMR0, PMMR2)**
    PMMR0
    **
    *
    Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1.
    *
    **
    The PMMR0, and PMMR2 register bits are cleared to zero following power up.
    ***
    Subsequent reset pulses will not clear the registers.
    The
    PSD935G2
    Functional
    Blocks
    (cont.)
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    *
    PLD
    array
    DBE
    PLD
    array
    ALE
    PLD
    **
    array
    CNTL2
    PLD
    **
    array
    CNTL1
    PLD
    **
    array
    CNTL0
    *
    PLD
    array
    Addr.
    1 = off
    1 = off
    1 = off
    1 = off
    1 = off
    1 = off
    PMMR2
    Bit 0 0 = Address A[7:0] inputs to the PLD AND array are connected.
    1 = Address A[7:0] inputs to the PLD AND array are disconnected, saving power.
    Note:
    In 80C51XA mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0].
    Bit 2 0 = Cntl0 input to the PLD AND array is connected.
    1 = Cntl0 input to PLD AND array is disconnected, saving power.
    Bit 3 0 = Cntl1 input to the PLD AND array is connected.
    1 = Cntl1 input to PLD AND array is disconnected, saving power.
    Bit 4 0 = Cntl2 input to the PLD AND array is connected.
    1 = Cntl2 input to PLD AND array is disconnected, saving power.
    Bit 5 0 = ALE input to the PLD AND array is connected.
    1 = ALE input to PLD AND array is disconnected, saving power.
    Bit 6 0 = DBE input to the PLD AND array is connected.
    1 = DBE input to PLD AND array is disconnected, saving power.
    *
    *
    Unused bits should be set to 0.
    **
    Refer to Table 14 the signals that are blocked on pins CNTL0-2.
    相關(guān)PDF資料
    PDF描述
    PSD935G2-70UI Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G2-90B81 Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G2-90B81I Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G2-90J Configurable Memory System on a Chip for 8-Bit Microcontrollers
    PSD935G2-90JI Configurable Memory System on a Chip for 8-Bit Microcontrollers
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