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    參數(shù)資料
    型號： PSD4235G2V-A-12J
    廠商： 意法半導體
    英文描述： Flash In-System-Programmable Peripherals for 16-Bit MCUs
    中文描述： Flash在系統(tǒng)可編程外設的16位微控制器
    文件頁數(shù)： 30/93頁
    文件大?。?/td> 503K
    代理商： PSD4235G2V-A-12J
    Preliminary Information
    PSD4000 Series
    27
    The
    PSD4000
    Functional
    Blocks
    (cont.)
    Level 1
    SRAM, I/O
    Level 2
    Secondary Flash Memory
    Highest Priority
    Lowest Priority
    Level 3
    Main Flash Memory
    Figure 5. Priority Level of Memory and I/OComponents
    9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
    The 80C51XA and compatible family of microcontrollers, can be configured to have
    separate address spaces for code memory (selected using PSEN) and data memory
    (selected using RD). Any of the memories within the PSD4000 can reside in either space
    or both spaces. This is controlled through manipulation of the VM register that resides in
    the PSD
    ’
    s CSIOP space.
    The VM register is set using PSDsoft to have an initial value. It can subsequently be
    changed by the microcontroller so that memory mapping can be changed on-the-fly.
    For example, you may wish to have SRAM and main Flash in Data Space at boot, and
    secondary Flash memory in Program Space at boot, and later swap main and secondary
    Flash memory. This is easily done with the VM register by using PSDsoft to configure it for
    boot up and having the microcontroller change it when desired.
    Table 11 describes the VM Register.
    Bit 7
    PIO_EN
    Bit 6* Bit 5*
    Bit 4
    FL_Data Boot_Data
    Bit 3
    Bit 2
    FL_Code
    Bit 1
    Bit 0
    Boot_Code SRAM_Code
    0 = disable
    PIO mode
    *
    *
    0 = RD
    can
    ’
    t
    access
    Flash
    0 = RD
    can
    ’
    t
    access
    Boot Flash
    0 = PSEN
    can
    ’
    t
    access
    Flash
    0 = PSEN
    can
    ’
    t
    access
    Boot Flash
    0 = PSEN
    can
    ’
    t
    access
    SRAM
    1= enable
    PIO mode
    *
    *
    1 = RD
    access
    Flash
    1 = RD
    access
    Boot Flash
    1 = PSEN
    access
    Flash
    1 = PSEN
    access
    Boot Flash
    1 = PSEN
    access
    SRAM
    Table 11. VM Register
    NOTE:
    Bits 6-5 are not used.
    相關PDF資料
    PDF描述
    PSD4235G2V-A-12JI Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G2V-A-12M Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G2V-A-12MI Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G2V-A-12U Flash In-System-Programmable Peripherals for 16-Bit MCUs
    PSD4235G2V-A-12UI Flash In-System-Programmable Peripherals for 16-Bit MCUs
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