VOS Input Offs" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� LT6200IS6-10#TRMPBF
寤犲晢锛� Linear Technology
鏂囦欢闋佹暩(sh霉)锛� 26/26闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC OP AMP 1.6GHZ R-R I/O SOT23-6
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 500
鏀惧ぇ鍣ㄩ鍨嬶細 绶╂矕鍣�
闆昏矾鏁�(sh霉)锛� 1
杓稿嚭椤炲瀷锛� 婊挎摵骞�
杞�(zhu菐n)鎻涢€熺巼锛� 450 V/µs
澧炵泭甯跺绌嶏細 1.6GHz
闆绘祦 - 杓稿叆鍋忓锛� 23µA
闆诲 - 杓稿叆鍋忕Щ锛� 2500µV
闆绘祦 - 闆绘簮锛� 20mA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 90mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 2.5 V ~ 12.6 V锛�±1.25 V ~ 6.3 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� SOT-23-6
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 TSOT-23-6
鍖呰锛� 甯跺嵎 (TR)
鍏跺畠鍚嶇ū锛� LT6200IS6-10#PBF
LT6200IS6-10#PBF-ND
9
62001ff
LT6200/LT6200-5
LT6200-10/LT6201
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VOS
Input Offset Voltage
VCM = Half Supply
VCM = V+
VCM = V鈥�
l
1.9
3.5
4.5
7.5
mV
Input Offset Voltage Match
(Channel-to-Channel) (Note 11)
VCM = 0V
VCM = V鈥� to V+
l
0.2
0.4
2
3.6
mV
VOS TC
Input Offset Voltage Drift (Note 8)
VCM = Half Supply
l
8.2
24
V/C
IB
Input Bias Current
VCM = Half Supply
VCM = V+
VCM = V鈥�
l
鈥�40
鈥�50
鈥�10
8
鈥�23
18
A
IB
IB Shift
VCM = V鈥� to V+
l
31
68
A
IB Match (Channel-to-Channel) (Note 11)
l
4
12
A
IOS
Input Offset Current
VCM = Half Supply
VCM = V+
VCM = V鈥�
l
1.3
1
3.5
10
15
A
AVOL
Large-Signal Gain
VO = 卤4.5V, RL = 1k
VO = 卤2V, RL = 100
l
46
7.5
80
13.5
V/mV
CMRR
Common Mode Rejection Ratio
VCM = V鈥� to V+
VCM = 鈥�2V to 2V
l
65
75
90
100
dB
CMRR Match (Channel-to-Channel) (Note 11) VCM = 鈥�2V to 2V
l
75
105
dB
PSRR
Power Supply Rejection Ratio
VS = 卤1.5V to 卤5V
l
60
65
dB
PSRR Match (Channel-to-Channel) (Note 6)
VS = 卤1.5V to 卤5V
l
60
100
dB
VOL
Output Voltage Swing LOW (Note 7)
No Load
ISINK = 5mA
ISINK = 20mA
l
16
60
170
75
125
310
mV
VOH
Output Voltage Swing HIGH (Note 7)
No Load
ISOURCE = 5mA
ISINK = 20mA
l
85
125
265
150
230
480
mV
ISC
Short-Circuit Current
l
卤60
卤90
mA
IS
Supply Current
Disabled Supply Current
VSHDN = 0.3V
l
25
1.6
29
2.1
mA
ISHDN
SHDN Pin Current
VSHDN = 0.3V
l
215
295
A
VL
VSHDN Pin Input Voltage LOW
l
0.3
V
VH
VSHDN Pin Input Voltage HIGH
l
V+ 鈥� 0.5
V
Shutdown Output Leakage Current
VSHDN = 0.3V
l
0.1
75
A
tON
Turn-On Time
VSHDN = 0.3V to 4.5V, RL = 100惟, VS = 5V
l
180
ns
tOFF
Turn-Off Time
VSHDN = 4.5V to 0.3V, RL = 100惟, VS = 5V
l
180
ns
SR
Slew Rate
AV = 鈥�1, RL = 1k, VO = 4V
LT6200, LT6201
l
31
44
V/s
AV = 鈥�10, RL = 1k, VO = 4V
LT6200-5
LT6200-10
l
125
260
180
370
V/s
FPBW
Full Power Bandwidth (Note 9)
VOUT = 3VP-P (LT6200-10)
l
27
39
MHz
elecTrical characTerisTics The 鈼� denotes the specifications which apply over 鈥�40掳C < T
A < 85掳C
temperature range. Excludes the LT6201 in the DD package (Note 3). VS = 卤5V, VCM = VOUT = 0V, VSHDN = OPEN, unless
otherwise noted. (Note 5)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime
Note 2: Inputs are protected by back-to-back diodes. If the differential
input voltage exceeds 0.7V, the input current must be limited to less
than 40mA. This parameter is guaranteed to meet specified performance
through design and/or characterization. It is not 100% tested.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
CT1206K30G VARISTOR 30VRMS 1206 SMD
LT6200IS6-10#TRM IC OP AMP 1.6GHZ R-R I/O SOT23-6
PPPC022LJBN-RC CONN FEMALE 4POS DL .1" R/A GOLD
AD820ARMZ-R7 IC OPAMP R-R FET-IN LP 8MSOP
960104-7102-AR CONN SOCKET SGL R/A 4POS GOLD
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
PIC18C601T-I/L 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 256KB 1536 RAM 26I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18C601T-I/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 256KB 1536 RAM 26I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18C658-E/L 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 52I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18C658-E/PT 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 52I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC18C658-I/L 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 32KB 1536 RAM 52I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT