參數(shù)資料
型號(hào)： PIC16F872-E/SP
廠商： Microchip Technology
文件頁數(shù)： 166/167頁
文件大小： 0K
描述： IC MCU CMOS 20MHZ 2K FLASH 28DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 15
系列： PIC® 16F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲(chǔ)器容量： 3.5KB（2K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 64 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x10b
振蕩器型： 外部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
98
8048C–AVR–02/12
ATtiny43U
12.9.12
TIMSK1 – Timer/Counter 1 Interrupt Mask Register
Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 2 – OCIEnB: Timer/Countern Output Compare Match B Interrupt Enable
When the OCIEnB bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Countern occurs, i.e., when the OCFnB bit is set in the Timer/Coun-
ter Interrupt Flag Register – TIFRn.
Bit 1 – OCIEnA: Timer/Countern Output Compare Match A Interrupt Enable
When the OCIEnA bit is written to one, and the I-bit in the Status Register is set, the
Timer/Countern Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Countern occurs, i.e., when the OCFnA bit is set in the
Timer/Counter n Interrupt Flag Register – TIFRn.
Bit 0 – TOIEn: Timer/Countern Overflow Interrupt Enable
When the TOIEn bit is written to one, and the I-bit in the Status Register is set, the Timer/Coun-
tern Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in
Timer/Countern occurs, i.e., when the TOVn bit is set in the Timer/Counter n Interrupt Flag Reg-
ister – TIFRn.
12.9.13
TIFR0 – Timer/Counter 0 Interrupt Flag Register
12.9.14
TIFR1 – Timer/Counter 1 Interrupt Flag Register
Bits 7:3 – Res: Reserved Bits
These bits are reserved and will always read zero.
Bit 2 – OCFnB: Output Compare Flag n B
The OCFnB bit is set when a Compare Match occurs between the Timer/Countern and the data
in OCRnB – Output Compare Registern B. OCFnB is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCFnB is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIEnB (Timer/Counter Compare B Match Interrupt Enable),
and OCFnB are set, the Timer/Countern Compare Match Interrupt is executed.
Bit
7654
3
2
1
0
––––
–
OCIE1B
OCIE1A
TOIE1
TIMSK1
Read/Write
RRRR
R
R/W
Initial Value
0000
0
Bit
765
432
10
–
OCF0B
OCF0A
TOV0
TIFR0
Read/Write
RR
RRR
R/W
Initial Value
0
Bit
765
432
10
–
OCF1B
OCF1A
TOV1
TIFR1
Read/Write
RR
RRR
R/W
Initial Value
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16F872-I/SO 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F872-I/SO 制造商:Microchip Technology Inc 功能描述:8BIT FLASH MCU SMD 16F872 SOIC28
PIC16F872-I/SOG 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O Lead Free Package RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F872-I/SP 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F872-I/SP 制造商:Microchip Technology Inc 功能描述:IC 8BIT FLASH MCU 16F872 SDIL28
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