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2009 Microchip Technology Inc.
DS39682E-page 169
PIC18F45J10 FAMILY
FIGURE 16-10:
I2C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESSING)
SDA
x
SCL
x
S
P
xIF
(P
IR1<
3>
or
P
IR3<
7>
)
BF
(
S
SPx
S
TA
T
<0
>)
S
1
2
3
4
56
7
8
9
1
2
3
4
5
6
7
89
1
2
3
4
5
7
8
9
P
1
0
A
9
A
8
A
7
A
6A
5
A
4A
3A
2A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
1
D
0
Re
ce
iv
eDa
ta
Byte
ACK
R/W
=
0
ACK
Re
ceive
F
irs
tB
yte
of
A
d
dr
ess
C
lea
re
di
n
s
o
ftw
a
re
D2
6
C
lear
ed
in
so
ftw
are
R
e
ce
iv
eS
econd
B
yte
of
A
ddre
ss
C
lea
re
db
yh
a
rd
w
a
re
w
he
n
SSP
xADD
is
u
p
d
at
e
d
w
ith
lo
w
byte
of
add
ress
UA
(
S
P
xS
TA
T
<
1>)
Cl
ock
is
h
e
ld
lo
w
u
n
til
updat
e
of
S
P
xA
D
has
ta
ken
pl
ac
e
UA
is
set
indicat
in
g
tha
t
the
S
P
xA
D
nee
ds
to
b
e
upda
ted
U
A
is
set
in
di
cati
ng
that
S
P
xA
D
nee
ds
to
b
e
update
d
C
le
ar
ed
by
har
d
w
a
re
w
hen
SSP
xADD
is
u
pd
a
te
d
wi
th
h
ig
h
by
te
of
addr
e
ss
S
SPxB
U
F
is
wr
itte
nwith
co
n
te
nt
so
fSS
Px
SR
D
um
m
y
re
a
do
fSS
Px
BUF
to
clear
B
F
flag
AC
K
CKP
12
3
4
5
7
8
9
D7
D6
D5
D4
D3
D1
D0
Re
ce
ive
Da
ta
B
yte
B
us
m
a
ste
r
term
inates
tran
sfer
D2
6
ACK
Cle
a
re
d
in
so
ftwa
re
Cle
a
re
d
in
so
ftwa
re
SS
PO
V
(
SSP
xC
O
N
1
<
6
>
)
S
SPO
V
is
s
et
because
S
P
xB
U
F
is
stil
lf
u
ll.
AC
K
is
no
tsent.
(C
K
P
do
es
not
reset
to
‘0
’w
hen
S
E
N
=
0
)
Clo
ck
is
h
e
ld
lo
w
u
n
til
upda
te
of
S
P
xA
D
ha
s
ta
ke
n
pl
ac
e