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    參數(shù)資料
    型號(hào): PIC16F627T-04I/SO
    廠商: Microchip Technology
    文件頁數(shù): 79/170頁
    文件大?。?/td> 0K
    描述: IC MCU FLASH 1KX14 COMP 18SOIC
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    標(biāo)準(zhǔn)包裝: 1,100
    系列: PIC® 16F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    連通性: UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 16
    程序存儲(chǔ)器容量: 1.75KB(1K x 14)
    程序存儲(chǔ)器類型: 閃存
    EEPROM 大小: 128 x 8
    RAM 容量: 224 x 8
    電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
    包裝: 帶卷 (TR)
    2003 Microchip Technology Inc.
    Preliminary
    DS40300C-page 15
    PIC16F62X
    3.2.2
    SPECIAL FUNCTION REGISTERS
    The SFRs are registers used by the CPU and Periph-
    eral functions for controlling the desired operation of
    the device (Table 3-1). These registers are static RAM.
    The special registers can be classified into two sets
    (core and peripheral). The SFRs associated with the
    “core” functions are described in this section. Those
    related to the operation of the peripheral features are
    described in the section of that peripheral feature.
    TABLE 3-1:
    SPECIAL REGISTERS SUMMARY BANK 0
    Address
    Name
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    Value on
    POR
    Reset(1)
    Details
    on Page
    Bank 0
    00h
    INDF
    Addressing this location uses contents of FSR to address data memory (not a physical register)
    xxxx xxxx
    01h
    TMR0
    Timer0 Module’s Register
    xxxx xxxx
    02h
    PCL
    Program Counter's (PC) Least Significant Byte
    0000 0000
    03h
    STATUS
    IRP
    RP1
    RP0
    TO
    PD
    ZDCC
    0001 1xxx
    04h
    FSR
    Indirect data memory address pointer
    xxxx xxxx
    05h
    PORTA
    RA7
    RA6
    RA5
    RA4
    RA3
    RA2
    RA1
    RA0
    xxxx 0000
    06h
    PORTB
    RB7
    RB6
    RB5
    RB4
    RB3
    RB2
    RB1
    RB0
    xxxx xxxx
    07h
    Unimplemented
    08h
    Unimplemented
    09h
    Unimplemented
    0Ah
    PCLATH
    Write buffer for upper 5 bits of program counter
    ---0 0000
    0Bh
    INTCON
    GIE
    PEIE
    T0IE
    INTE
    RBIE
    T0IF
    INTF
    RBIF
    0000 000x
    0Ch
    PIR1
    EEIF
    CMIF
    RCIF
    TXIF
    CCP1IF
    TMR2IF
    TMR1IF
    0000 -000
    0Dh
    Unimplemented
    0Eh
    TMR1L
    Holding register for the Least Significant Byte of the 16-bit TMR1
    xxxx xxxx
    0Fh
    TMR1H
    Holding register for the Most Significant Byte of the 16-bit TMR1
    xxxx xxxx
    10h
    T1CON
    T1CKPS1
    T1CKPS0
    T1OSCEN
    T1SYNC
    TMR1CS
    TMR1ON
    --00 0000
    11h
    TMR2
    TMR2 module’s register
    0000 0000
    12h
    T2CON
    TOUTPS3
    TOUTPS2
    TOUTPS1
    TOUTPS0
    TMR2ON
    T2CKPS1
    T2CKPS0
    -000 0000
    13h
    Unimplemented
    14h
    Unimplemented
    15h
    CCPR1L
    Capture/Compare/PWM register (LSB)
    xxxx xxxx
    16h
    CCPR1H
    Capture/Compare/PWM register (MSB)
    xxxx xxxx
    17h
    CCP1CON
    CCP1X
    CCP1Y
    CCP1M3
    CCP1M2
    CCP1M1
    CCP1M0
    --00 0000
    18h
    RCSTA
    SPEN
    RX9
    SREN
    CREN
    ADEN
    FERR
    OERR
    RX9D
    0000 -00x
    19h
    TXREG
    USART Transmit data register
    0000 0000
    1Ah
    RCREG
    USART Receive data register
    0000 0000
    1Bh
    Unimplemented
    1Ch
    Unimplemented
    1Dh
    Unimplemented
    1Eh
    Unimplemented
    1Fh
    CMCON
    C2OUT
    C1OUT
    C2INV
    C1INV
    CIS
    CM2
    CM1
    CM0
    0000 0000
    Legend:
    — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
    shaded = unimplemented
    Note
    1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
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