參數(shù)資料
型號： SMM764FCR3
廠商： Summit Microelectronics, Inc.
英文描述： Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩
中文描述： 四通道有源直流輸出控制器，監(jiān)視器，Marginer和音序器的序列連接⑩
文件頁數(shù)： 22/33頁
文件大?。?/td> 392K
代理商： SMM764FCR3
SMM764
Preliminary Information
Summit Microelectronics, Inc
2098 1.1 6/29/2005
22
SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I
2
C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (t
HIGH
)
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing. The address byte is
comprised of a 4-bit device type identifier SA[3:0]
(slave address) and a 3-bit bus address BA[2:0]. The
remaining bit indicates either a read or a write
operation. Refer to Table 1 for a description of the
address bytes used by the SMM764.
The device type identifier for the memory array is
generally set to 1010
BIN
following the industry standard
for a typical nonvolatile memory. There is an option to
change the identifier to 1011
BIN
allowing it to be used
on a bus that may be occupied by other memory
devices. The configuration registers are grouped with
the memory array and thus use 1010
BIN
or 1011
BIN
as
the device type identifier. The command and status
registers as well as the 10-bit ADC are accessible with
the separate device type identifier of 1001
BIN
.
The bus address bits BA[1:0] are programmed into the
configuration registers. Bus address bit BA[2] can be
programmed as either 0 or biased by the A2 pin. The
bus address accessed in the address byte of the serial
data stream must match the setting in the SMM764
and on the A2 pin.
Any access to the SMM764 on the I
2
C bus will
temporarily halt the monitoring function. This does not
affect the ADOC function, which will continue
functioning and control the DC outputs. This is true
not only during the monitor mode, but also during
power-on and power-off sequencing when the device
is monitoring the channels to determine if they have
turned on or turned off.
The SMM764 halts the monitor function from when it
acknowledges the address byte until a valid stop is
received.
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 13, 14, 15, 17 and 19. A Start
condition followed by the address byte is provided by
the host; the SMM764 responds with an Acknowledge;
the host then responds by sending the memory
address pointer or configuration register address
pointer; the SMM764 responds with an acknowledge;
the host then clocks in on byte of data. For memory
and configuration register writes, up to 15 additional
bytes of data can be clocked in by the host to write to
consecutive addresses within the same page. After
the last byte is clocked in and the host receives an
Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
READ
The address pointer for the configuration registers,
memory, command and status registers and ADC
registers must be set before data can be read from the
SMM764. This is accomplished by a issuing a dummy
write command, which is simply a write command that
is not followed by a Stop condition. The dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figures 16, 18 and 21 for an
illustration of the read sequence.
I
2
C PROGRAMMING INFORMATION
相關(guān)PDF資料
PDF描述
SMM764FCR4 Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩
SMM764FCR5 Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩
SMM764FCR6 Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SMM764FCR4 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩
SMM764FCR5 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩
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SMM764FR0 制造商:SUMMIT 制造商全稱:SUMMIT 功能描述:Four-Channel Active DC Output Controller, Monitor, Marginer and Sequencer with Sequence-Link⑩
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