參數(shù)資料
    型號: PIC16C710-04/SS
    廠商: Microchip Technology
    文件頁數(shù): 56/177頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 512X14 A/D 20SSOP
    產(chǎn)品培訓模塊: Asynchronous Stimulus
    標準包裝: 67
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    外圍設(shè)備: 欠壓檢測/復位,POR,WDT
    輸入/輸出數(shù): 13
    程序存儲器容量: 896B(512 x 14)
    程序存儲器類型: OTP
    RAM 容量: 36 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
    振蕩器型: 外部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
    包裝: 管件
    配用: 309-1016-ND - ADAPTER 20-SSOP TO 18-DIP
    149
    7593L–AVR–09/12
    AT90USB64/128
    The setup of the OC2x should be performed before setting the Data Direction Register for the
    port pin to output. The easiest way of setting the OC2x value is to use the Force Output Com-
    pare (FOC2x) strobe bit in Normal mode. The OC2x Register keeps its value even when
    changing between Waveform Generation modes.
    Be aware that the COM2x1:0 bits are not double buffered together with the compare value.
    Changing the COM2x1:0 bits will take effect immediately.
    16.5
    Compare Match Output unit
    The Compare Output mode (COM2x1:0) bits have two functions. The Waveform Generator uses
    the COM2x1:0 bits for defining the Output Compare (OC2x) state at the next compare match.
    Also, the COM2x1:0 bits control the OC2x pin output source. Figure 16-4 shows a simplified
    schematic of the logic affected by the COM2x1:0 bit setting. The I/O Registers, I/O bits, and I/O
    pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
    (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the
    OC2x state, the reference is for the internal OC2x Register, not the OC2x pin.
    Figure 16-4. Compare Match Output unit, schematic.
    The general I/O port function is overridden by the Output Compare (OC2x) from the Waveform
    Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out-
    put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
    Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visi-
    ble on the pin. The port override function is independent of the Waveform Generation mode.
    The design of the Output Compare pin logic allows initialization of the OC2x state before the out-
    put is enabled. Note that some COM2x1:0 bit settings are reserved for certain modes of
    PORT
    DDR
    DQ
    OCnx
    pin
    OCnx
    DQ
    Waveform
    generator
    COMnx1
    COMnx0
    0
    1
    D
    ATA
    B
    U
    S
    FOCnx
    clk
    I/O
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