參數資料
型號: PIC12F635-I/MD
廠商: Microchip Technology
文件頁數: 48/74頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 1KX14 8DFN
產品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 91
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數: 5
程序存儲器容量: 1.75KB(1K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VDFN 裸露焊盤
包裝: 管件
產品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC164326-ND - MODULA SKT PM3 20QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
Micrel, Inc.
KSZ8841-PMQL
October 2007
52
M9999-100407-1.5
Wakeup Frame 3 Byte Mask 0 Register (Offset 0x0254): WF3BM0
This register contains the first 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the first byte
of the Wake up frame 3; setting bit 15 selects the 16th byte of the Wake up frame 3.
Bit
Default
R/W
Description
15 - 0
--
RW
WF3BM0
Wake up Frame 3 Byte Mask 0
The first 16bytes mask of a wake up frame 3 pattern.
Wakeup Frame 3 Byte Mask 1 Register (Offset 0x0256): WF3BM1
This register contains the next 16bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 3; setting bit 15 selects the 32nd byte of the Wake up frame 3.
Bit
Default
R/W
Description
15 - 0
--
RW
WF3BM1
Wake up Frame 3 Byte Mask 1
The next 16bytes mask covering bytes 17 to 32 of a wake up frame 3
pattern.
Wakeup Frame 3 Byte Mask 2 Register (Offset 0x0258): WF3BM2
This register contains the next 16bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 3; setting bit 15 selects the 48th byte of the Wake up frame 3.
Bit
Default
R/W
Description
15 - 0
--
RW
WF3BM2
Wake up Frame 3 Byte Mask 2
The next 16bytes mask covering bytes 33 to 48 of a wake up frame 3
pattern.
Wakeup Frame 3 Byte Mask 3 Register (Offset 0x025A): WF3BM3
This register contains the last 16bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 3; setting bit 15 selects the 64th byte of the Wake up frame 3.
Bit
Default
R/W
Description
15 - 0
--
RW
WF3BM2
Wake up Frame 3 Byte Mask 3
The last 16 bytes mask covering bytes 49 to 64 of a wake up frame 3
pattern.
Chip ID and Enable Register (Offset 0x0400): CIDER
This register contains the chip ID, and the chip enables control.
Bit
Default
R/W
Description
15-8
0x88
RO
Family ID
Chip family ID
7-4
0x05
RO
Chip ID
0x05 is assigned to KSZ8841-PMQL
3-1
000
RO
Revision ID
0
-
RW
Start Controller
1 = Start the chip operation
0 = Stop the chip operation
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