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參數(shù)資料
| 型號： | PCA9540D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 2-channel I2C multiplexer |
| 中文描述： | PCA9 SERIES, 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO8 |
| 封裝： | 3.90 MM, PLASTIC, MS-012, SOT-96-1, SO-8 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 110K |
| 代理商： | PCA9540D |
Philips Semiconductors
Product specification
PCA9540
2-channel I
2
C multiplexer
1999 Dec 15
5
Acknowledge
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits
is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an
extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock
pulse, set-up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of
the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
SCL FROM
MASTER
SW00368
DATA OUTPUT
BY RECEIVER
1
2
8
9
S
START condition
clock pulse for
acknowledgement
acknowledge
not acknowledge
Figure 4. Acknowledgement on the I
2
C-bus
1
1
0
0
0
0
slave address
fixed
hardware selectable
SW00564
1
Figure 5. Slave address
1
2
SCL
SDA
3
4
5
6
7
8
SDA
S
0
A
A
1
1
1
0
0
0
0
SLAVE ADDRESS
start condition
R/W
acknowledge
from slave
acknowledge
from slave
t
pv
NEW CHANNEL
9
B0
X
X
X
B1
CONTROL REGISTER
PREVIOUS CHANNEL
P
SW00498
1
2
3
4
5
6
7
8
9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B2
X
X
Figure 6. WRITE control register
SDA
S
1
A
NA
1
1
1
0
0
0
0
start condition
R/W
acknowledge
from slave
X
X
B1
CONTROL REGISTER
P
stop condition
last byte
SW00499
SLAVE ADDRESS
no acknowledge
from master
B0
B2
X
X
X
Figure 7. READ control register
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