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參數(shù)資料
| 型號(hào)： | P4C1682-35FSMB |
| 廠商： | PYRAMID SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 4K X 4 STANDARD SRAM, 35 ns, PDFP24 |
| 封裝： | DFP-24 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 121K |
| 代理商： | P4C1682-35FSMB |
P4C1681, P4C1682
Page 4 of 10
Document # SRAM109 REV B
Notes:
5.
WE is HIGH for READ cycle.
6.
CE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with,
CE
transition LOW.
-12
-15
-20
-25
-35
Min Max
Min
Max Min Max
t
RC
Read Cycle Time
12
15
20
25
35
ns
t
AA
Address Access
12
15
20
25
35
ns
Time
t
AC
Chip Enable
12
15
20
25
35
ns
Access Time
t
OH
Output Hold from
2
3
ns
Address Change
t
LZ
Chip Enable to
2
3
ns
Output in Low Z
t
HZ
Chip Disable to
6
7
9
10
15
ns
Output in High Z
t
RCS
Read Command
0
ns
Setup Time
t
RCH
Read Command
0
ns
Hold Time
t
PU
Chip Enable to
0
ns
Power Up Time
t
PD
Chip Disable to
12
15
20
25
ns
Power Down Time
READ CYCLE NO. 1 (ADDRESS controlled)(5, 6)
READ CYCLE NO. 2 (
CE controlled)(5, 7)
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Symbol
Parameter
Unit
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC = 5V ± 10%, All Temperature Ranges)
(2)
1552 Tbl 10
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