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參數(shù)資料
| 型號(hào)： | OR2T26A-6M352 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 7500pF; Working Voltage (Vdc)[max]: 50V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1812; Termination: Solder Coated SnPb; Body Dimensions: 0.180" x 0.125" x 0.080"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate |
| 中文描述： | 現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁(yè)數(shù)： | 1/192頁(yè) |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T26A-6M352 |
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ORCA
Series 2
Field-Programmable Gate Arrays
Data Sheet
June 1999
Features
s
High-performance, cost-effective, low-power
0.35 m CMOS technology (OR2CxxA), 0.3 m CMOS
technology (OR2TxxA), and 0.25 m CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
s
High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
s
Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
s
Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
s
Eight 3-state buffers per PFU for on-chip bus structures
s
Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
s
Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
s
Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
s
Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
s
Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
s
Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacrificing
performance
s
Upward bit stream compatible with the
ORCA ATT2Cxx/
ATT2Txx series of devices
s
Pinout-compatible with new
ORCA Series 3 FPGAs
s
TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
s
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
s
Built-in boundary scan (
IEEE*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
s
Multiple configuration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
s
Full PCI bus compliance for all devices
s
Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with
ORCA Foundry
Development System support (for back-end implementa-
tion)
s
New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (VDD5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI sys-
tems
*
IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1
. ORCA Series 2 FPGAs
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.
Device
Usable
Gates*
# LUTs
Registers
Max User
RAM Bits
User
I/Os
Array Size
OR2C04A/OR2T04A
4,800—11,000
400
6,400
160
10 x 10
OR2C06A/OR2T06A
6,900—15,900
576
9,216
192
12 x 12
OR2C08A/OR2T08A
9,400—21,600
784
724
12,544
224
14 x 14
OR2C10A/OR2T10A
12,300—28,300
1024
16,384
256
16 x 16
OR2C12A/OR2T12A
15,600—35,800
1296
20,736
288
18 x 18
OR2C15A/OR2T15A/OR2T15B
19,200—44,200
1600
25,600
320
20 x 20
OR2C26A/OR2T26A
27,600—63,600
2304
36,864
384
24 x 24
OR2C40A/OR2T40A/OR2T40B
43,200—99,400
3600
57,600
480
30 x 30
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2T26A-6T432I | Field-Programmable Gate Arrays |
| OR2T26A-7BA208 | Field-Programmable Gate Arrays |
| OR2T26A-7BA208I | Field-Programmable Gate Arrays |
| OR2T26A-7BA240 | Field-Programmable Gate Arrays |
| OR2T26A-7BA240I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T26A6PS208-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T26A6PS208I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T26A6PS240-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T26A6PS240I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2304 LUT 326 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T26A6S208-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 Use LatticeEC RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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