參數(shù)資料
型號(hào)： NT1GT64U8HA0B-3C
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 128M X 64 DDR DRAM MODULE, 0.45 ns, DMA240
封裝： DIMM-240
文件頁數(shù)： 8/20頁
文件大?。?/td> 311K
代理商： NT1GT64U8HA0B-3C
NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green)
NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green)
512MB: 64M x 64 / 1GB: 128M x 64
Unbuffered DDR2 SDRAM DIMM
REV 1.1
16
03/2005
NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TA = 0 °C ~ 70 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
-5A
-37B
-3C
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tAC
DQ output access time from CK/CK
-0.6
+0.6
-0.5
+0.5
-0.45
+0.45
ns
tDQSCK
DQS output access time from CK/CK
-0.5
+0.5
-0.45
+0.45
-0.4
+0.4
ns
tCH
CK high-level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCL
CK low-level width
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tHP
Minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
tCH
or
tCL
tCH
or
tCL
tCH
or
tCL
tCK
CL=3
5
8
3.75
8
3
8
ns
tCK
Clock cycle time
CL=4, 5
5
8
3.75
8
3
8
ns
tDH
DQ and DM input hold time
0.275
0.225
0.175
ns
tDS
DQ and DM input setup time
0.15
0.1
ns
tIPW
Input pulse width
0.6
ns
tDIPW
DQ and DM input pulse width (each input)
0.35
ns
tHZ
Data-out high-impedance time from CK/CK
tAC (max)
tAC
ns
tLZ
Data-out low-impedance time from CK/CK
2tAC (min) tAC (max)
2tAC
(min)
tAC (max)
tAC
ns
tDQSQ
DQS-DQ skew (DQS & associated DQ signals)
0.35
0.3
0.24
ns
tQHS
Data hold Skew Factor
0.45
0.4
0.34
ns
tQH
Data output hold time from DQS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tCK
tDQSS
Write command to 1st DQS latching transition
-0.25
+0.25
-0.25
+0.25
-0.25
+0.25
tCK
tDQSL,(H)
DQS input low (high) pulse width
(write cycle)
0.35
tCK
tDSS
DQS falling edge to CK setup time
(write cycle)
0.2
tCK
tDSH
DQS falling edge hold time from CK
(write cycle)
0.2
tCK
tMRD
Mode register set command cycle time
2
tCK
tWPST
Write postamble
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tWPRE
Write preamble
0.35
tCK
tIH
Address and control input hold time
0.475
0.375
0.275
ns
tIS
Address and control input setup time
0.35
0.25
0.2
ns
tRPRE
Read preamble
0.9
1.1
0.9
1.1
0.9
1.1
tCK
tRPST
Read postamble
0.4
0.6
0.4
0.6
0.4
0.6
tCK
tRAS
Active to Precharge command
45
120,000
40
120,000
45
120,000
ns
tRRD
Active bank A to Active bank B command
7.5
ns
tCCD
CAS to CAS
2
tCK
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