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參數資料
| 型號： | NM25C040NX |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| 中文描述： | 4K的位串行CMOS EEPROM的（串行外設接口（SPI），同步總線） |
| 文件頁數： | 8/10頁 |
| 文件大小： | 115K |
| 代理商： | NM25C040NX |
8
www.fairchildsemi.com
NM25C040 Rev. D.1
N
(
SCK
SI
SO
CS
D0
D1
D2
DS012401-12
Functional Description
(Continued)
FIGURE 10. Write Sequence
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRITE cycle is still in progress and Bit 0 =
0 indicates that the WRITE cycle has ended. During the WRITE
programming cycle (Bit 0 = 1) only the READ STATUS REGIS-
TER instruction is enabled.
The NM25C040 is capable of a 4 byte PAGE WRITE operation.
After receipt of each byte of data the two low order address bits are
internally incremented by one. The seven high order bits of the
address will remain constant. If the master should transmit more
than 4 bytes of data, the address counter will “roll over,” and the
previously loaded data will be reloaded. See Figure 11.
FIGURE 11. 4 Byte Page Write
The WRSR command requires the following sequence. The CS
line is pulled low to select the device and then the WRSR op-code
is transmitted on the SI line followed by the data to be pro-
grammed. See Figure 12.
FIGURE 12. Write Status Register
CS
SI
SO
Write
Op-Code
Byte
Addr (n)
Data
(n)
Data
(n + 1)
Data
(n + 2)
Data
(n + 3)
CS
SI
SO
WRSR
Op-Code
SR Data
xxxxBP1BP0xx
DS012401-13
DS012401-14
BP0
SCK
SI
SO
CS
DS012401-15
FIGURE 13. Start WRSR Condition
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
If the device is not WRITE enabled, the device will ignore the
WRITE instruction and return to the standby state when CS is
forced high. A new CS falling edge is required to re-initialize the
serial communication.
WRITE STATUS REGISTER (WRSR):
The WRITE STATUS
REGISTER (WRSR) instruction is used to program the non-
volatile status register Bits 2 and 3 (BP0 and BP1). The WRITE
PROTECT (WP) pin must be held high and two separate instruc-
tions must be executed. The chip must first be write enabled via
the WRITE ENABLE instruction and then a WRSR instruction
must be executed.
Note that the first four bits are don’t care bits followed by BP1 and
BP0 then two additional don’t care bits. Programming will start
after the CS pin is forced back to a high level. As in the WRITE
instruction the LOW to HIGH transition of the CS pin must occur
during the SCK low time immediately after clocking in the last don’t
care bit. See Figure 13.
The READY/BUSY status of the device can be determined by
executing a READ STATUS REGISTER (RDSR) instruction. Bit 0
= 1 indicates that the WRSR cycle is still in progress and Bit 0 =
0 indicates that the WRSR cycle has ended.
At the completion of a WRITE cycle the device is automatically
returned to the write disable state.
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相關代理商/技術參數 |
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| NM25C040VM8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
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| NM25C040VMT8 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:SPI Serial EEPROM |
| NM25C040VMT8X | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:4K-Bit Serial CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) |
| NM25C040VN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SPI Serial EEPROM |
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