參數(shù)資料
型號(hào)： TCS59SM704AFT-70
廠商： Toshiba Corporation
英文描述： 8M×4Banks×4Bits Synchronous DRAM(4組8M×4位同步動(dòng)態(tài)RAM)
中文描述： 8米× 4Banks × 4Bits同步DRAM（4組8米× 4位同步動(dòng)態(tài)RAM）的
文件頁數(shù)： 8/49頁
文件大?。?/td> 2421K
代理商： TCS59SM704AFT-70
TC59SM716/08/04AFT/AFTL-70,-75,-80
2000-02-08 8/49
(9)
These parameters account for the number of clock cycles and depend on the operating frequency of the
clock, as follows:
the number of clock cycles
=
specified value of timing / clock period
(count fractions as a whole number)
(10)
t
CH
is the pulse width of CLK measured from the positive edge to the negative edge referenced to V
IH
(min). t
CL
is the pulse width of CLK measured from the negative edge to the positive edge referenced to
V
IL
(max).
(11)
Power-up Sequence
Power-up must be performed in the following sequence.
1)
Power must be applied to V
CC
and V
CCQ
(simultaneously) while all input signals are held in the
“NOP” state. The CLK signals must be started at the same time.
2)
After power-up a pause of at least 200
μ
s is required. It is required that DQM and CKE signals
must be held “High” (V
CC
levels) to ensure that the DQ output is in High-impedance state.
3)
All banks must be precharged.
4)
The Mode Register Set command must be asserted to initialize the Mode Register.
5)
A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitry of
the device.
The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles.
(12)
AC Latency Characteristics
CKE to clock disable (CKE Latency)
1
DQM to output in High-Z (Read DQM Latency)
2
DQM to input data delay (Write DQM Latency)
0
Write command to input data (Write Data Latency)
0
CS
to Command input (
CS
Latency)
0
CL
=
2
2
Precharge to DQ Hi-Z Lead time
CL
=
3
3
CL
=
2
1
Precharge to Last Valid data out
CL
=
3
2
CL
=
2
2
Burst Stop Command to DQ Hi-Z Lead time
CL
=
3
3
CL
=
2
1
Burst Stop Command to Last Valid data out
CL
=
3
2
Cycle
CL
=
2
BL
+
t
RP
Read with Autoprecharge Command to Active/Ref Command
CL
=
3
BL
+
t
RP
CL
=
2
BL
+
t
RP
Write with Autoprecharge Command to Active/Ref Command
CL
=
3
BL
+
t
RP
Cycle
+
ns
相關(guān)PDF資料
PDF描述
TCS59SM708AFT-70 4M×4Banks×8Bits Synchronous DRAM(4組4M×8位同步動(dòng)態(tài)RAM)
TCS59SM708AFT-75 4M×4Banks×8Bits Synchronous DRAM(4組4M×8位同步動(dòng)態(tài)RAM)
TCS59SM708AFT-80 4M×4Banks×8Bits Synchronous DRAM(4組4M×8位同步動(dòng)態(tài)RAM)
TCS59SM708AFTL-70 4M×4Banks×8Bits Synchronous DRAM(4組4M×8位同步動(dòng)態(tài)RAM)
TCS59SM708AFTL-75 4M×4Banks×8Bits Synchronous DRAM(4組4M×8位同步動(dòng)態(tài)RAM)
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