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參數(shù)資料
| 型號(hào)： | NCV612SQ50T1 |
| 廠(chǎng)商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 100 mA CMOS Low Iq Voltage Regulator in an SC70-5 |
| 中文描述： | 5 V FIXED POSITIVE REGULATOR, PDSO5 |
| 封裝： | MINIATURE, SC-88A, SOT-353, SC-70, 5 PIN |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 61K |
| 代理商： | NCV612SQ50T1 |
NCP612, NCV612
http://onsemi.com
8
APPLICATIONS INFORMATION
A typical application circuit for the NCP612/NCV612 is
shown in Figure 1, front page.
Input Decoupling (C1)
A 1.0
recommended and should be connected close to the
NCP612/NCV612 package. Higher values and lower ESR
will improve the overall line transient response.
TDK capacitor: C2012X5R1C105K, or C1608X5R1A105K
F capacitor either ceramic or tantalum is
Output Decoupling (C2)
The NCP612/NCV612 is a stable regulator and does not
require any specific Equivalent Series Resistance (ESR) or
a minimum output current. Capacitors exhibiting ESRs
ranging from a few m up to 5.0
The minimum decoupling value is 1.0 F and can be
augmented to fulfill stringent load transient requirements.
The regulator accepts ceramic chip capacitors as well as
tantalum capacitors. Larger values improve noise rejection
and load regulation transient response.
TDK capacitor: C2012X5R1C105K, C1608X5R1A105K,
or C3216X7R1C105K
can thus safely be used.
Enable Operation
The enable pin will turn on the regulator when pulled high
and turn off the regulator when pulled low. These limits of
threshold are covered in the electrical specification section
of this data sheet. If the enable is not used then the pin should
be connected to V
in
.
Hints
Please be sure the Vin and Gnd lines are sufficiently wide.
When the impedance of these lines is high, there is a chance
to pick up noise or cause the regulator to malfunction.
Set external components, especially the output capacitor,
as close as possible to the circuit, and make leads as short as
possible.
Thermal
As power across the NCP612/NCV612 increases, it might
become necessary to provide some thermal relief. The
maximum power dissipation supported by the device is
dependent upon board design and layout. Mounting pad
configuration on the PCB, the board material and also the
ambient temperature effect the rate of temperature rise for
the part. This is stating that when the NCP612/NCV612 has
good thermal conductivity through the PCB, the junction
temperature will be relatively low with high power
dissipation applications.
The maximum dissipation the package can handle is
given by:
TJ(max)
PD
TA
RJA
If junction temperature is not allowed above the
maximum 125
°
C, then the NCP612/NCV612 can dissipate
up to 330 mW @ 25
°
C.
The power dissipated by the NCP612/NCV612 can be
calculated from the following equation:
Ptot
[Vin* Ignd(Iout)]
or
[Vin
Vout] * Iout
VinMAX
Ptot
Vout*Iout
Ignd
Iout
If an 100 mA output current is needed then the ground
current from the data sheet is 40
NCP612/NCV612 (3.0 V), the maximum input voltage will
then be 6.0 V (Limited by maximum input voltage).
A. For an
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