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參數(shù)資料
| 型號(hào)： | NCP2830MUTXG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUDIO CLASS D 20UQFN |
| 產(chǎn)品變化通告： | Product Obsolescence 24/Jan/2011 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | D 類 |
| 輸出類型： | 1-通道（單聲道） |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 1.2W x 1 @ 8 歐姆 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 特點(diǎn)： | 差分輸入，關(guān)閉 |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 20-UQFN（3x3） |
| 封裝/外殼： | 20-UFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
NCP2830
http://onsemi.com
3
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
Description
20
VB_IN
I
This pin must be externally connection in a star configuration with Pin n°15. The Cout filtering
(10 mF/6.3 V/0603) capacitor must be connected as close as possible to the connection point.
3
AGND
P
Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of
track length. Thus, a star connection is required.
9
PGND_C
P
Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of
track length. Thus, a star connection is required.
17
PGND_D
P
Ground. These pins must be connected separately to the dedicated Ground plane with a minimum of
track length. Thus, a star connection is required.
4, 12
AVDD
PVDD
P
These pins are dedicated to the signal connection for the battery input. They must be connected to the
power source (ie lithium/Ion battery) in a star mode. It must be decoupled by a low ESR ceramic
capacitor. (4.7
mF/6.3 V/0603). The use of a 4 or more layers board is advised. In that case, a dedicated
plane for this battery voltage is mandatory.
1
INP
I
Positive audio input of the fully differential filterless Class D Audio Amplifier
2
INM
I
Negative audio input of the fully differential filterless Class D Audio Amplifier
16
OUTM
O
Negative audio output of the fully differential filterless Class D Audio Amplifier
18
OUTP
O
Positive audio output of the fully differential filterless Class D Audio Amplifier
5
WM
I
Wire Mode pin: When a low level is applied to this pin, the device operates in Normal mode (VB = 5 V
typ.). In case of a high level, it switches to a Wire Mode (VB = VDD)
6
SD
I
Shutdown input. The device enters in shutdown mode when a low level is applied on this pin.
7
GS
I
Gain Select Input. When a low level is applied to this pin, an internal 2 V/V gain is setup. In case of a
high level, it switches to an internal 4 V/V gain.
8
C2N
P
One side of the external charge pump capacitor is connected to this pin, associated with C2P. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2
mF/6.3 V/0603
recommended).
10
C1N
P
One side of the external charge pump capacitor is connected to this pin, associated with C1P. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2
mF/6.3V/0603
recommended).
13
C2P
P
One side of the external charge pump capacitor is connected to this pin, associated with C2N. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2
mF/6.3 V/0603
recommended).
14
C1P
P
One side of the external charge pump capacitor is connected to this pin, associated with C1N. Using a
low ESR ceramic capacitor is recommended to optimize charge pump efficiency (2.2
mF/6.3 V/0603
recommended).
15
VB_OUT
O
This pin must be externally connection in a star configuration with Pin n°20. The Cout filtering
(10
mF/6.3 V/0603) capacitor must be connected as close as possible to the connection point. This VB
input is dedicated to supply the internal power stages. Thus, it must be connected to Cout with the
lowest impedance connection.
11
RES1
I
Reserved for production. Must be connected to GND plane in final application
19
RES2
I
Reserved for production. Must be connected to GND plane in final application
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