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參數(shù)資料
| 型號： | NAND99W3M1AZBC5F |
| 廠商： | NUMONYX |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA137 |
| 封裝： | 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-137 |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 724K |
| 代理商： | NAND99W3M1AZBC5F |
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NANDxxxxMx
Signals description
17/32
2.6
Flash memory Read Enable (R)
The Read Enable, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
2.7
Flash memory Write Enable (WF)
The Write Enable input, WF, controls writing to the command interface, input address, and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down, a minimum recovery time of 10 s is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
2.8
Flash memory Write Protect (WP)
The Write Protect pin is an input that provides hardware protection against unwanted
program or erase operations. When Write Protect is Low, VIL, the device does not accept
any program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
2.9
Flash memory Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that can be used to identify if the P/E/R
controller is currently active.
When Ready/Busy is Low, VOL, this signifies that a read, program, or erase operation is in
progress. When the operation completes, Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
2.10
Flash memory VDDF supply voltage
VDDF provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program, and erase).
An internal voltage detector disables all functions whenever VDDF is below the VLKO
threshold to protect the device from any involuntary program/erase operations during power
transitions.
Each device in a system should have VDDF decoupled with a 0.1 F capacitor, and the PCB
track widths should be sufficient to carry the required program and erase currents
2.11
Flash memory VSSF ground
Ground, VSSF, is the reference for the power supply. It must be connected to the system
ground.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NANDA8R3N0AZBB5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| NANDA8R3N1AZBC5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| NANDA8R3N1AZBC5F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| NANDA8R3N8AZBB5E | 制造商:Micron Technology Inc 功能描述:128MX8/16MX16 MCP PLASTIC WIRELESS TEMP PBF TFBGA 1.8V - Trays |
| NANDA8R3N8AZBB5F | 制造商:Micron Technology Inc 功能描述:128MX8/16MX16 MCP PLASTIC WIRELESS TEMP PBF TFBGA 1.8V - Tape and Reel |
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