參數(shù)資料
型號: NAND99W3M1AZBC5F
廠商: NUMONYX
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA137
封裝: 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-137
文件頁數(shù): 2/33頁
文件大小: 724K
代理商: NAND99W3M1AZBC5F
Description
NANDxxxxMx
Table 4.
Signal names (TFBGA107, TFBGA137 and TFBGA149 packages)
NAN
D
flash
memory
Signal
Function
Direction
I/O0-I/O7
Data inputs/outputs for x8/x16 devices
Input/output
I/O8-I/O15
Data inputs/outputs for x16 devices
Input/output
AL
Address Latch Enable
Input
CL
Command Latch Enable
Input
EF
Chip Enable
Input
R
Read Enable
Input
RB
Ready/Busy (open-drain output)
Output
WF
Write Enable
Input
WP
Write Protect
Input
VDDF
Supply voltage
Power supply
VSSF
Ground
LPSD
RAM
A0-A12
Row address: A0-A12
Column address:
– A0-A8 (256 Mbits and 512 Mbits x32)
– A0-A9 (512 Mbits x16)
Auto-precharge flag: A10
Input
BA0-BA1
Bank address
Input
DQ0-DQ15
Data inputs/outputs, ×16/×32
Input/output
DQ16-DQ31
Data inputs/outputs, ×32
Input/output
K, K
Clock
Input
KE
Clock Enable
Input
ED
Chip Select
Input
WD
Write Enable
Input
RAS
Row Address Strobe
Input
CAS
Column Address Strobe
Input
DQM0
DQ Mask Enable (controls DQ0-DQ7, ×16/×32)
Input/output
DQM1
DQ Mask Enable (controls DQ8-DQ15, ×16/×32)
Input/output
DQM2
DQ Mask Enable (controls DQ16-DQ23, ×32)
Input/output
DQM3
DQ Mask Enable (controls DQ24-DQ31, ×32)
Input/output
UDQM
Upper Data Read Strobe (DDR x16)
Input/output
LDQM
Lower Data Write Strobe (DDR x16)
Input/output
VSSD
Ground
VSSQD
Input/output ground
Ground
NC
Not connected internally
N/A
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