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參數(shù)資料
| 型號： | NAND99W3M1AZBC5F |
| 廠商： | NUMONYX |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA137 |
| 封裝： | 10.50 X 13 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-137 |
| 文件頁數(shù)： | 10/33頁 |
| 文件大小： | 724K |
| 代理商： | NAND99W3M1AZBC5F |
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Signals description
NANDxxxxMx
2.12
LPSDRAM address inputs (A0-A12)
The A0-A12 address inputs are used to select the row or column to be made active. If a row
is selected, all thirteen address inputs, A0-A12, are used. If a column is selected, only the
least significant address inputs, A0-A8 (256-Mbit device and 512-Mbit x32 device) or A0-A9
(512-Mbit x16 device), are used. In this latter case, A10 determines whether auto precharge
is used. If A10 is High (set to ‘1’) during read or write, the operation includes an auto
precharge cycle. If A10 is Low (set to ‘0’) during read or write, the cycle does not include an
auto precharge cycle.
2.13
LPSDRAM bank select address inputs (BA0-BA1)
The select address inputs of the BA0 and BA1 banks are used to select the bank to be
made active.
The following are the necessary settings when selecting the addresses:
l
The device must be enabled
l
Row Address Strobe, RAS, must be Low, VIL
l
Column Address Strobe, CAS, must be High, VIH
l
W must be High, VIH
The address inputs are latched on the rising edge of the clock signal, K.
2.14
LPSDRAM data inputs/outputs (DQ0-DQ15 and DQ16-DQ31)
The DQ16-DQ31 data inputs/outputs are available only in the NAND99W3M1 and
NANDA9W3M1, where the bus width is ×32.The data inputs/outputs output the data stored
at the selected address during a read operation, or are used to input the data during a write
operation.
2.15
LPSDRAM Chip Select (ED)
The Chip Select input, ED, activates the memory state machine, address buffers, and
decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.16
LPSDRAM Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with address inputs A8-A0 (256-
Mbit device and 512-Mbit x32 device) or A9-A0 (512-Mbit x16 device) and BA1-BA0, to
select the starting column location prior to a read or write operation.
2.17
LPSDRAM Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with address inputs A12-A0 and BA1-
BA0 to select the starting address location prior to a read or write operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NANDA8R3N0AZBB5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| NANDA8R3N1AZBC5E | 制造商:Micron Technology Inc 功能描述:WIRELESS - Trays |
| NANDA8R3N1AZBC5F | 制造商:Micron Technology Inc 功能描述:WIRELESS - Tape and Reel |
| NANDA8R3N8AZBB5E | 制造商:Micron Technology Inc 功能描述:128MX8/16MX16 MCP PLASTIC WIRELESS TEMP PBF TFBGA 1.8V - Trays |
| NANDA8R3N8AZBB5F | 制造商:Micron Technology Inc 功能描述:128MX8/16MX16 MCP PLASTIC WIRELESS TEMP PBF TFBGA 1.8V - Tape and Reel |
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