參數(shù)資料
型號： NAND512W3A2C
廠商： 意法半導(dǎo)體
英文描述： 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
中文描述： 512兆位，528 Byte/264字的頁面，1.8V/3V，NAND閃存芯片
文件頁數(shù)： 8/51頁
文件大?。?/td> 517K
代理商： NAND512W3A2C
Bus operations
NAND512-A2C
16/51
4.5
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
4.6
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
Bus operations
Bus Operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
1.
Only for x16 devices.
Command Input
VIL
VIH
Rising
X(2)
2.
WP must be VIH when issuing a program or erase command.
Command
X
Address Input
VIL
VIH
VIL
VIH
Rising
X
Address
X
Data Input
VIL
VIH
Rising
X
Data Input
Data Output
VIL
Fallin
g
VIH
X
Data Output
Write Protect
X
VIL
XX
Standby
VIH
X
XXXX
X
Table 6.
Address Insertion, x8 devices(1)(2)
1.
A8 is set Low or High by the 00h or 01h Command, see Section 6.1: Pointer operations.
2.
Any additional address input cycles will be ignored.
Bus
Cycle
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
2nd
A16
A15
A14
A13
A12
A11
A10
A9
3rd
A24
A23
A22
A21
A20
A19
A18
A17
4th
VIL
A25
Table 7.
Address Insertion, x16 devices(1)(2)
1.
A8 is Don’t Care in x16 devices.
2.
Any additional address input cycles will be ignored.
Bus
Cycle
I/O8-
I/O15
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
X
A7
A6
A5
A4
A3
A2
A1
A0
2nd
X
A16
A15
A14
A13
A12
A11
A10
A9
3rd
X
A24
A23
A22
A21
A20
A19
A18
A17
4th(4)
X
VIL
A25
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