參數(shù)資料
型號(hào)： NAND512R3A2CN6F
廠商： 意法半導(dǎo)體
英文描述： 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
中文描述： 512兆位，528 Byte/264字的頁(yè)面，1.8V/3V，NAND閃存芯片
文件頁(yè)數(shù)： 7/51頁(yè)
文件大?。?/td> 517K
代理商： NAND512R3A2CN6F
NAND512-A2C
Bus operations
15/51
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations, for a summary.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 17 and Table 20 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory address. Three bus cycles are
required to input the addresses for the 128Mb and 256Mb devices and four bus cycles are
required to input the addresses for the 512Mb and 1Gb devices (refer to Table 6 and
Table 7, Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 18 and Table 20 for details of the timings requirements.
4.3
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 19, Table 20, and Table 21 for details of the timings requirements.
4.4
Data Output
Data Output bus operations are used to read: the data in the memory array, the Status
Register, the Electronic Signature and the Serial Number.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 20 and Table 21 for details of the timings requirements.
相關(guān)PDF資料
PDF描述
NAND512R3A2C 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2CN6F 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2CZA6E 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2CZA6F 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2C 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND512R3A2CZA6E 功能描述:IC FLASH 512MBIT 63VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ
NAND512R3A2CZA6F 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 1.8V 512Mbit 64M x 8bit 15us 63-Pin VFBGA T/R
NAND512R3A2DDI6 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film
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NAND512R3A2SE06 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film
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