- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296674 > NAND512R3A2CN6F (意法半導(dǎo)體) 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories PDF資料下載
參數(shù)資料
| 型號： | NAND512R3A2CN6F |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| 中文描述： | 512兆位，528 Byte/264字的頁面，1.8V/3V，NAND閃存芯片 |
| 文件頁數(shù)： | 5/51頁 |
| 文件大?。?/td> | 517K |
| 代理商： | NAND512R3A2CN6F |
第1頁第2頁第3頁第4頁當(dāng)前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁
NAND512-A2C
Signal descriptions
13/51
3
Signal descriptions
See Figure 1: Logic diagram, and Table 3: Signal names, for a brief overview of the signals
connected to this device.
3.1
Inputs/Outputs (I/O0-I/O7)
Input/Outputs 0 to 7 are used to input the selected address, output the data during a Read
operation or input a command or data during a Write operation. The inputs are latched on
the rising edge of Write Enable. I/O0-I/O7 are left floating when the device is deselected or
the outputs are disabled.
3.2
Inputs/Outputs (I/O8-I/O15)
Input/Outputs 8 to 15 are only available in x16 devices. They are used to output the data
during a Read operation or input data during a Write operation. Command and Address
Inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
Address Latch Enable (AL)
The Address Latch Enable activates the latching of the Address inputs in the Command
Interface. When AL is high, the inputs are latched on the rising edge of Write Enable.
3.4
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the Command inputs in the Command
Interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
3.5
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and read
circuitry. When Chip Enable is low, VIL, the device is selected.
If Chip Enable goes High (VIH) while the device is busy, the device remains selected and
does not go into standby mode.
3.6
Read Enable (R)
The Read Enable, R, controls the sequential data output during Read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| NAND512R3A2C | 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND512R4A2CN6F | 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND512R4A2CZA6E | 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND512R4A2CZA6F | 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND512R4A2C | 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NAND512R3A2CZA6E | 功能描述:IC FLASH 512MBIT 63VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| NAND512R3A2CZA6F | 制造商:Micron Technology Inc 功能描述:SLC NAND Flash Parallel 1.8V 512Mbit 64M x 8bit 15us 63-Pin VFBGA T/R |
| NAND512R3A2DDI6 | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
| NAND512R3A2DZA6E | 功能描述:IC FLASH 512MBIT 63VFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:1,000 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (512 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.7 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-MFP 包裝:帶卷 (TR) |
| NAND512R3A2SE06 | 制造商:Micron Technology Inc 功能描述:NAND - Gel-pak, waffle pack, wafer, diced wafer on film |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。