參數(shù)資料
型號： NAND04GW3C2AN6F
廠商： NUMONYX
元件分類： PROM
英文描述： 512M X 8 FLASH 3V PROM, 45 ns, PDSO48
封裝： 12 X 20 MM, LEAD FREE, PLASTIC, TSOP-48
文件頁數(shù)： 7/51頁
文件大?。?/td> 500K
代理商： NAND04GW3C2AN6F
NAND04GA3C2A, NAND04GW3C2A
4 Bus operations
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus Operations, for a summary.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command Input
Command Input bus operations are used to give commands to the memory. Commands are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They are latched on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 13 and Table 19 for details of the timings requirements.
4.2
Address Input
Address Input bus operations are used to input the memory addresses. Five bus cycles are
required to input the addresses (refer to Table 6: Address insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 14 and Table 19 for details of the timings requirements.
4.3
Data Input
Data Input bus operations are used to input the data to be programmed.
Data is only accepted when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 15 and Table 19 for details of the timing requirements.
4.4
Data Output
Data Output Bus operations are used to read: the data in the memory array, the Status
Register, the Electronic Signature and the Unique Identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 16 and Table 20 for details of the timings requirements.
相關(guān)PDF資料
PDF描述
NAND512R3A2CN6E 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R3A2CN6F 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R3A2C 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2CN6F 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
NAND512R4A2CZA6E 512 Mbit, 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
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