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參數(shù)資料
| 型號： | SC403MLTRT |
| 廠商： | Semtech |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 741K |
| 描述： | IC REG DL BCK/LINEAR SYNC 32MLPQ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| 拓?fù)洌?/td> | 降壓（降壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 1MHz |
| 電壓/電流 - 輸出 1： | 可調(diào)至 0.75V，6A |
| 電壓/電流 - 輸出 2： | 可調(diào)至 0.75V，200mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 3 V ~ 28 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-MLPQ（5x5） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | SC403MLDKR |
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SC403
17
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage V
OUT
is offset by the output ripple according to the
following equation.
2
V
R
R
1
75
.
0
V
RIPPLE
2
1
OUT
When a large capacitor is placed in parallel with R1 (C
TOP
)
V
OUT
is shown by the following equation.
2
TOP
1
2
1
2
2
TOP
1
RIPPLE
2
1
OUT
C
R
R
R
R
1
)
C
R
(
1
2
V
R
R
1
75
.
0
V
Enable and Power Save Input
The EN/PSV input is used to enable or disable the switch-
ing regulator. When EN/PSV is low (grounded), the switch-
ing regulator is off and in its lowest power state. When off,
the output of the switching regulator soft-discharges the
output into a 15& internal resistor via the V
OUT
pin. When
EN/PSV is allowed to float, the pin voltage will float to 33%
of the voltage at VDD. The switching regulator turns on
with PSAVE (power save) disabled and all switching is in
forced continuous mode.
When EN/PSV is high (above 45% of the voltage at VDD),
the switching regulator turns on with ultrasonic power-
save enabled. The ultrasonic PSAVE operation maintains a
minimum switching frequency of 25kHz, for applications
with stringent audio requirements.
Forced Continuous Mode Operation
The SC403 operates the switcher in FCM (Forced
Continuous Mode) by floating the EN/PSV pin (see Figure
4). In this mode one of the power MOSFETs is always on,
with no intentional dead time other than to avoid cross-
conduction. This feature results in uniform frequency
across the full load range with the trade-off being poor
efficiency at light loads due to the high-frequency switch-
ing of the MOSFETs. DH is the gate signal driving the
upper MOSFET. DL is the lower gate signal driving the
lower MOSFET.
FB Ripple
Voltage (V
FB
)
FB threshold
DL
DH
Inductor
Current
DC Load Current
DH on-time is triggered when
V
FB
reaches the FB Threshold.
(750mV)
On-time
(T
ON
)
DL drives high when on-time is completed.
DL remains high until V
FB
falls to the FB threshold.
Figure 4 Forced Continuous Mode Operation
Ultrasonic PSAVE Operation
The SC403 provides ultrasonic PSAVE operation at light
loads, with the minimum operating frequency fixed at
25kHz. This is accomplished using an internal timer that
monitors the time between consecutive high-side gate
pulses. If the time exceeds 40祍, DL drives high to turn the
low-side MOSFET on. This draws current from V
OUT
through
the inductor, forcing both V
OUT
and V
FB
to fall. When V
FB
drops to the 750mV threshold, the next DH on-time is trig-
gered. After the on-time is completed the high-side
MOSFET is turned off and the low-side MOSFET turns on.
The low-side MOSFET remains on until the inductor
current ramps down to zero, at which point the low-side
MOSFET is turned off.
Applications Information (continued)
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