參數(shù)資料
型號: MX25U8035ZUI-25G
廠商: MACRONIX INTERNATIONAL CO LTD
元件分類: PROM
英文描述: 2M X 4 FLASH 1.8V PROM, PDSO8
封裝: 4 X 4 MM, 0.60 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MO-252, USON-8
文件頁數(shù): 6/56頁
文件大?。?/td> 2467K
代理商: MX25U8035ZUI-25G
14
MX25U4035
MX25U8035
P/N: PM1394
REV. 1.1, JUN. 30, 2009
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 1. "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ,RES, REMS,
REMS2 and REMS4 the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data
being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, BE32K, BE,
CE, PP, 4PP, CP, RDP, DP, ENSO, EXSO, and WRSCUR, the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
SCLK
MSB
CPHA
shift in
shift out
SI
0
1
CPOL
0
(Serial mode 0)
(Serial mode 3) 1
SO
SCLK
MSB
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