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參數(shù)資料
| 型號： | MX25U8035ZUI-25G |
| 廠商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分類： | PROM |
| 英文描述： | 2M X 4 FLASH 1.8V PROM, PDSO8 |
| 封裝： | 4 X 4 MM, 0.60 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MO-252, USON-8 |
| 文件頁數(shù)： | 54/56頁 |
| 文件大?。?/td> | 2467K |
| 代理商： | MX25U8035ZUI-25G |
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7
MX25U4035
MX25U8035
P/N: PM1394
REV. 1.1, JUN. 30, 2009
Table 1. Additional Feature Comparison
GENERAL DESCRIPTION
The MX25U4035 are 4,194,304 bit serial Flash memory, which is configured as 524,288 x 8 internally. When it is in
two or four I/O read mode, the structure becomes 2,097,152 bits x 2 or 1,048,576 bits x 4. The MX25U8035 are 8,388,608
bit serial Flash memory, which is configured as 1,048,576 x 8 internally. When it is in two or four I/O read mode, the
structure becomes 4,194,304 bits x 2 or 2,097,152 bits x 4. When it is in two or four I/O read mode, the structure
becomes 8,388,608 bits x 2 or 4,194,304 bits x 4. The MX25U4035/MX25U8035 feature a serial peripheral inter-
face and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus
signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device
is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-
put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and RESET#/HOLD# pin become
SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U4035/MX25U8035 provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for Continuously program mode, and erase command is executes on sector (4K-byte),
block (32K-byte), or block (64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 5uA DC current.
The MX25U4035/MX25U8035 utilizes MXIC's proprietary memory cell, which reliably stores memory contents even
after typical 100,000 program and erase cycles.
Additional
Features
Part
Name
Protection and
Security
Read Performance
Identifier
Flexible
Block
Protection
(BP0-BP3)
512-bit
secured
OTP
2 I/O
Read
4 I/O
Read
RES
(command:
AB hex)
REMS
(command:
90 hex)
REMS2
(command:
EF hex)
REMS4
(command:
DF hex)
RDID
(command:
9F hex)
MX25U4035
V
33 (hex)
C2 33 (hex)
(if ADD=0)
C2 33 (hex)
(if ADD=0)
C2 33 (hex)
(if ADD=0)
C2 25 33
(hex)
MX25U8035
V
34 (hex)
C2 34 (hex)
(if ADD=0)
C2 34 (hex)
(if ADD=0)
C2 34 (hex)
(if ADD=0)
C2 25 34
(hex)
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