參數(shù)資料
型號(hào)： MX25U8035ZUI-25G
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： PROM
英文描述： 2M X 4 FLASH 1.8V PROM, PDSO8
封裝： 4 X 4 MM, 0.60 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MO-252, USON-8
文件頁(yè)數(shù)： 15/56頁(yè)
文件大?。?/td> 2467K
代理商： MX25U8035ZUI-25G
22
MX25U4035
MX25U8035
P/N: PM1394
REV. 1.1, JUN. 30, 2009
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(9) 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status
Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,
and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency
fQ. The first address byte can be at any location. The address is automatically increased to the next higher address
after each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The ad-
dress counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the fol-
lowing address/dummy/data out will perform as 4-bit instead of previous 1-bit.
The sequence of issuing 4READ instruction is: CS# goes low→ sending 4READ instruction→ 24-bit address in-
terleave on SIO3, SIO2, SIO1 & SIO0→ 6 dummy cycles → data out interleave on SIO3, SIO2, SIO1 & SIO0→ to
end 4READ operation can use CS# to high at any time during data out (Please refer to figure 18 for 4 x I/O Read
Mode Timing Waveform).
Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low→sending
4 READ instruction→3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 →performance enhance toggling bit
P[7:0]→ 4 dummy cycles →data out still CS# goes high → CS# goes low (reduce 4 Read instruction) →24-bit ran-
dom access address (Please refer to figure 19 for 4x I/O read enhance performance mode timing waveform).
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-
wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(10) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see table of memory organization) is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on SI
→CS# goes high. (Please refer to Figure 23)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the sec-
tor.
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