參數(shù)資料
型號(hào)： MX25U8035ZUI-25G
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類(lèi)： PROM
英文描述： 2M X 4 FLASH 1.8V PROM, PDSO8
封裝： 4 X 4 MM, 0.60 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MO-252, USON-8
文件頁(yè)數(shù)： 11/56頁(yè)
文件大?。?/td> 2467K
代理商： MX25U8035ZUI-25G
19
MX25U4035
MX25U8035
P/N: PM1394
REV. 1.1, JUN. 30, 2009
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (Please refer to Figure 13)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, volatile bits, indicate the protected area (as
defined in table 2) of the device to against the program/erase instruction without hardware protection mode being
set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to
be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE),
Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP2:BP0)
set to 0, the CE instruction can be executed).
The BP3, BP2, BP1, BP0 bits default value are "1". Which is protected.
QE bit. The Quad Enable (QE) bit, volatile bit, performs Quad when it is reset to "0" (factory default) to enable WP#
or is set to "1" to enable Quad SIO2 and SIO3.
SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#/
SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only.
The SRWD bit defaults to be "0".
Status Register
Note 1: see the table 2 "Protected Area Size".
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
BP3
(level of
protected
block)
BP2
(level of
protected
block)
BP1
(level of
protected
block)
BP0
(level of
protected
block)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=status
register write
disable
1=Quad
Enable
0=not Quad
Enable
(note 1)
1=write
enable
0=not write
enable
1=write
operation
0=not in write
operation
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