參數(shù)資料
型號： MX25L1605DMI-12G
廠商： MACRONIX INTERNATIONAL CO LTD
元件分類： PROM
英文描述： 8M X 2 FLASH 2.7V PROM, PDSO16
封裝： 0.300 INCH, ROHS COMPLIANT, MS-013, SOP-16
文件頁數(shù)： 55/56頁
文件大?。?/td> 3202K
代理商： MX25L1605DMI-12G
8
MX25L1605D
MX25L3205D
MX25L6405D
P/N: PM1290
REV. 1.5, APR. 29, 2009
HOLD FEATURES
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-
rial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure 1.
Figure 1. Hold Condition Operation
PROGRAM/ERASE ACCELERATION
To activate the program/erase acceleration function requires ACC pin connecting to 9.5~10.5V voltage (see Figure
2), and then to be followed by the normal program/erase process. By utilizing the program/erase acceleration opera-
tion, the performances are improved as shown on table of "ERASE AND PROGRAM PERFORMACE".
After power-up ready, it should wait 10ms at least to apply VHH(9.5~10.5V) on the WP#/ACC pin.
Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM
Note: tVHH (VHH Rise and Fall Time) min. 250ns
HOLD#
CS#
SCLK
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
ACC
9.5~10.5V
tVHH
VHH
VIL or VIH
tVHH
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