參數(shù)資料
型號(hào): MT90221AL
廠商: Mitel Networks Corporation
英文描述: Quad IMA/UNI PHY Device
中文描述: 四IMA的/單向物理層設(shè)備
文件頁(yè)數(shù): 14/114頁(yè)
文件大?。?/td> 304K
代理商: MT90221AL
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
MT90221
6
101, 103,
111, 113
TXCKi/o
[3:0]
I/O
PCM Interface Transmit Clock 3-0.
This pin is an input for PCM Modes 2, 4, 5 and
7. It is an output for Interface Modes 1, 3, 6 and 8 (see Section 4.2, PCM System
Interface Modes).
It is the clock for serial PCM data transmission of the T1 and E1 framers. The TXCK
source is software selectable and can be either one of the eight RXCK or one of the
four REFCK signals. It is used for internal transmit timing and should be connected
to the Transmit Clock of the framer.
1. The TXCK is 4.096 MHz for ST-BUS applications.
2. For generic PCM Interfaces (non ST-BUS or asynchronous line termination),
these outputs can be programmed to provide either a 1.544 MHz (T1) or 2.048
MHz (T1 or E1) clock.
98, 106,
108, 115
TXSYNCio
[3:0]
I/O
Transmit Line 8KHz Frame Pulse 3-0
. This pin is an input for Interface Modes 2,
4, 5 and 7. It is an output for Interface Modes 1, 3, 6 and 8 (see PCM Section 4.2,
PCM System Interface Modes).
It is the 8 kHz reference used as transmit synchronization for the PCM system
interface. When an output, the TXSYNC is generated from the TXCK signal and is
independent from other TXSYNC signals. Two output modes can be programmed:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32 channel
frame of the ST-BUS interface at DSTi and DSTo lines (see Figure 25 - ST-BUS
Timing Diagram for this sync pulse). The frame pulse is typically received through
the RXSYNC[0] pin.
2. For generic PCM Interfaces, it can be programmed to generate either a positive
or negative pulse polarity that lines up with the first bit of the PCM system interface.
135, 142,
144, 150
RXSYNCi
[3:0]
I
Receive line 8KHz Frame Pulse 3-0
. This signal represents the 8 KHz reference
received from the incoming T1 or E1 line. The MT90221 can be programmed to
accept different 8 KHz pulse formats at this input.
1. For ST-BUS applications, it is a low going pulse (F0), which delimits the 32
channel frame of ST-BUS interface at DSTi and DSTo lines. See STBUS timing
diagram for this sync pulse.
2. For generic PCM Interfaces, it can be programmed to accept either positive or
negative pulse polarities.
138, 140,
146, 148
RXCKi
[3:0]
I
PCM Interface Receive Clock 3-0.
This input line represents the clock for the
receive serial PCM data of the T1 and E1 framers. The T1 or E1 frequency value to
be received at this input clock is defined by the user through an internal register.
1. For ST-BUS applications, input pin RXCKi receives the 4.096 MHz signal.
2. For generic PCM Interfaces, these inputs can be programmed to accept either a
1.544 MHz (T1) or 2.048 MHz (T1 or E1) clock.
154, 155
PLLREF
[1:0]
O
Output reference to an external PLL.
See 4.3 Description of the PCM Interface
for details.
158, 159,
160, 161
REFCK
[3:0]
I
Input reference clock inputs 3 to 0.
Receive the de-jittered transmit clock
reference to be internally routed to the T1/E1 framer transmit clocks (output pins
TXCK[3:0]. See “Description of the PCM Interface” on page 23. for more details.
80, 83 85,
87, 89, 92,
94 96,
117,118,
124, 125,
126, 127,
133, 134
NC
No Connect.
Suggest using external pull-up to reduce noise.
Pin Description (continued)
Pin #
Name
I/O
Description
相關(guān)PDF資料
PDF描述
MT9041B T1/E1 System Synchronizer
MT9041BP T1/E1 System Synchronizer
MT9041 Multiple Output Trunk PLL
MT9041AP IC REG LDO 150MA 5.0V 0.5% 8SOIC
MT9042C Multitrunk System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90222 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device
MT90222AG 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays
MT90222AG2 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays
MT90223AG 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays
MT90223AG2 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays