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參數(shù)資料
| 型號(hào)： | MT90221 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Quad IMA/UNI PHY Device |
| 中文描述： | 四IMA的/單向物理層設(shè)備 |
| 文件頁(yè)數(shù)： | 43/114頁(yè) |
| 文件大?。?/td> | 304K |
| 代理商： | MT90221 |
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MT90221
35
six types of interrupts are reported (in the six least
significant bits of the
IRQ Link Status
registers) for
each link:
Bit 5 latched: reports that an ICP Cell with
changes was received on a RX PCM link.
Bit 4 latched: reports an IV (ICP Cell violation)
condition on a RX PCM link.
Bit 3 latched: reports an LODS (Link is Out of
Delay Synchronization) condition on a RX PCM
link.
Bit 2 latched: reports an LIF (Loss of IMA
Frame) condition on a RX PCM link.
Bit 1 latched: reports an LCD (Loss of Cell
Delineation) condition on a RX PCM link.
Bit 0 (LSB) is a status bit. It reports an interrupt for
an overflow condition in one or more of the 12
counters associated with the link. It is also used to
report an overflow condition in the UTOPIA RX FIFO
associated with a PCM link in UNI mode. If enabled,
a counter generates an interrupt request when it
overflows (i.e starts over from 0 after reaching the
maximum counter value). 6.1 Counter Block
paragraph for more details on the operation of the
counters. These 13 sources of overflow can be
identified through the
IRQ Link FIFO Overflow
and
IRQ UTOPIA FIFO Overflow
status registers. Refer
to section 6.2.3 IRQ Link UNI Overflow and IRQ
UTOPIA Input UNI Overflow Status Registers for
more details.
Reading the
IRQ Link Status
register does not clear
the source of interrupt. The bit 0 status is reset by
any one of the following procedures:
disabling (masking) the IRQ for this specific
counter
clearing the overflow status bit in the
IRQ Link
UNI Overflow
and
IRQ UTOPIA UNI Overflow
Status
registers
disabling the interrupt in the
RX UTOPIA Link
FIFO Overflow Enable
or in the corresponding
Link (in UNI mode) Counter registers.
Bits 1, 2, 3, 4 and 5 of the
IRQ Link Status
register
are latches that report the source of an interrupt.
Writing a ’0’ these bits will reset the status bit (will
reset the latch). Writing ’0’ to bit 0 has no effect on
the status bit.
Writing a ’1’ has no effect on the bits 0 to 5 of the
IRQ Link Status
register.
Each one of these six interrupt sources can be
enabled by writing a ’1’ in the
IRQ Link Enable
register to the bit corresponding to the interrupt
source.
In some situations, an interrupt source can be
masked as part of an interrupt service routine. This
makes it possible to detect further interrupts of
higher priority. For example, if an interrupt for a
counter is received, the source of the interrupt can
be masked by writing 0 to the bit 0 and then starting
a separate process, outside of the Interrupt Service
Routine. The independent process would read,
reload and re-enable the counter to produce another
interrupt service request, if necessary. At the end of
this process, the enable bit in the
IRQ Link Enable
register would be set to ’1’ to detect any future
interrupt requests.
6.2.2.1
Bit 7 and 6 of IRQ Link 0 Status and IRQ
Link 0 Enable Registers
Bits 7 (MSB) and 6 of the
IRQ Link 0 Status
register
have a special meaning.
Bit 7 reports an overflow condition in any of the
counters or UTOPIA RX FIFOs associated with one
of the four IMA Groups. Refer to 6.2.4 IRQ IMA
Group Overflow Status and Enable Registers for
more details. Bit 7 is a status bit and is cleared by
disabling the IRQ for this specific counter or
disabling (masking) the FIFO overflow condition by
writing to the
RX UTOPIA IMA Group FIFO
Overflow Enable
register.
Bit 6 is used to report the following two event types:
the ICP cell internal transfer is complete (reported
by any IMA Group TX ICP Cell Ready bit)
the end of an IMA frame on the reference link of an
IMA Group
The second type of event assists in implementing the
software counter required to verify that Group Status
and Control field information is sent for at least 2
consecutive IMA frames.
The
independently by writing to the
TX ICP Cell Handler
Enable
register.
eight
interrupt
sources
are
enabled
There is also an associated Control/Status register
(
TX ICP Cell Handler
register) that reports the
interrupt source and the state of the transfer of an
ICP Cell or the occurrence of the end of an IMA
frame. The Frame status bits are cleared by writing 0
to the bit. The Ready bit is set to 1 when the transfer
is complete. Bit 6 is a latched bit in the
IRQ Link 0
Status
register and is cleared by overwriting it with
0.
Each of these two interrupt sources can be masked
by writing a ’1’ to the bit corresponding to the
interrupt source in the
IRQ Link 0 Enable
register.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90221AL | Quad IMA/UNI PHY Device |
| MT9041B | T1/E1 System Synchronizer |
| MT9041BP | T1/E1 System Synchronizer |
| MT9041 | Multiple Output Trunk PLL |
| MT9041AP | IC REG LDO 150MA 5.0V 0.5% 8SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
| MT90222AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA - Trays |
| MT90222AG2 | 制造商:Microsemi Corporation 功能描述:ATM IMA 40MBPS 2.5V 384BGA /BAKE/DRYPACK - Trays |
| MT90223AG | 制造商:Microsemi Corporation 功能描述:ATM IMA 80MBPS 2.5V 384BGA - Trays |
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