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參數(shù)資料
| 型號： | MT90220 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | IC, MICREL LDO 5A ADJ VLT REG TO-2 |
| 中文描述： | 八路IMA的/單向物理層設(shè)備 |
| 文件頁數(shù)： | 8/116頁 |
| 文件大?。?/td> | 306K |
| 代理商： | MT90220 |
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MT90220
vi
List of Tables
Pin Description ....................................................................................................................................................... 4
Pinout Summary..................................................................................................................................................... 7
Table 1 - IDCR Integration Register Value........................................................................................................... 12
Table 2 - ICP Cell Description.............................................................................................................................. 13
Table 3 - Cell Acquisition Time............................................................................................................................. 16
Table 4 - Differential Delay for Various Memory Configuration............................................................................ 19
Table 5 - Conversion Factors Time/Cell (msec)................................................................................................... 20
Table 6 - PCM Modes........................................................................................................................................... 24
Table 7 - PCM Clock and Mapping Options......................................................................................................... 24
Table 8 - T1Channel Mapping Using 3 Channels Every 4 Channels................................................................... 25
Table 9 - T1 Channel Mapping Using 24 Consecutive Channels......................................................................... 26
Table 10 - Channel Mapping from ST-BUS to E1 ................................................................................................ 26
Table 11 - Register Summary............................................................................................................................... 38
Table 12 - UTOPIA Input Link Address Registers................................................................................................ 41
Table 13 - UTOPIA Input Group Address Registers............................................................................................. 41
Table 14 - UTOPIA Input Link PHY Enable Register ........................................................................................... 41
Table 15 - UTOPIA Input Group PHY Enable Register........................................................................................ 42
Table 16 - Utopia Input Control Register.............................................................................................................. 42
Table 17 - UTOPIA Output Link Address Registers............................................................................................. 42
Table 18 - UTOPIA Output Group Address Registers......................................................................................... 43
Table 19 - UTOPIA Output Link PHY Enable Register......................................................................................... 43
Table 20 - UTOPIA Output Group PHY Enable Register..................................................................................... 43
Table 21 - RX UTOPIA IMA Group FIFO Overflow Enable Register.................................................................... 44
Table 22 - RX UTOPIA Link FIFO Overflow Enable Register .............................................................................. 44
Table 23 - TX Cell RAM Control Register............................................................................................................ 45
Table 24 - TX UTOPIA FIFO Level Register........................................................................................................ 45
Table 25 - TX FIFO Length Definition Register 1................................................................................................. 45
Table 26 - TX FIFO Length Definition Register 2................................................................................................ 45
Table 27 - TX FIFO Length Definition Register 3................................................................................................. 46
Table 28 - TX FIFO Length Definition Register 4................................................................................................ 46
Table 29 - TX FIFO Length Definition Register 5................................................................................................ 46
Table 30 - TX FIFO Length Definition Register 6................................................................................................. 46
Table 31 - TX Group Control Mode Registers..................................................................................................... 47
Table 32 - TX Link ID Registers .......................................................................................................................... 47
Table 33 - TX ICP Cell Offset Registers.............................................................................................................. 47
Table 34 - TX IDCR Integration Registers............................................................................................................ 48
Table 35 - TX Link Control Registers ................................................................................................................... 48
Table 36 - TX IMA Control Registers................................................................................................................... 49
Table 37 - TX IMA Mode Status Register............................................................................................................ 49
Table 38 - TX ICP Cell Handler Register.............................................................................................................. 50
Table 39 - TX ICP Cell Interrupt Enable Register................................................................................................ 50
Table 40 - TX ICP Cell Registers ........................................................................................................................ 51
Table 41 - RX Link Control Registers.................................................................................................................. 52
Table 42 - Cell Delineation Register.................................................................................................................... 52
Table 43 - Loss of Delineation Register ............................................................................................................... 52
Table 44 - IMA Frame Delineation Register........................................................................................................ 53
Table 45 - RX OAM Label Register..................................................................................................................... 53
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90220AL | Octal IMA/UNI PHY Device |
| MT90221 | Quad IMA/UNI PHY Device |
| MT90221AL | Quad IMA/UNI PHY Device |
| MT9041B | T1/E1 System Synchronizer |
| MT9041BP | T1/E1 System Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
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