參數(shù)資料
型號(hào): MT90220
廠商: Mitel Networks Corporation
英文描述: IC, MICREL LDO 5A ADJ VLT REG TO-2
中文描述: 八路IMA的/單向物理層設(shè)備
文件頁(yè)數(shù): 41/116頁(yè)
文件大?。?/td> 306K
代理商: MT90220
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)當(dāng)前第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)
MT90220
33
6.0 Support Blocks
6.1
The MT90220 includes 112 24-bit counters to
provide statistical information on the device’s
operation. All the counters are cleared by a hardware
reset. A maskable interrupt can be generated when
the counter overflows.
Counter Block
A predetermined value can also be loaded in a
counter. This feature can be used to generate an
interrupt after a specified number of cells is
processed. Counter values are incremented by 1 for
every event occurrence and, when the count goes to
all 1’s, will overflow (to all 0’s).
6.1.1
There are four counters associated with the each of
the 12 UTOPIA Inputs (from ATM layer to the
MT90220) for a total of 48 counters. These counters
record the following information:
the total number of cells received at the
UTOPIA Input I/F
the total number of Idle Cells received at the
UTOPIA Input I/F, removed or not
the total number of Unassigned Cells received
at the UTOPIA Input I/F, removed or not
the number of cells having a single or multiple
bit error in the HEC, removed or not but not
including the cells where the HEC is corrected
UTOPIA Input I/F counters
6.1.2
There are four counters associated with the each of
the eight transmit PCM links for a total of 32 Transmit
counters. These counters record the following
information:
the total number of cells sent through the PCM
link
the total number of Idle/Filler cells sent through
the PCM link
the total number of Stuff cells sent through the
PCM link
Transmit PCM I/F Counters
the total number of ICP cells sent through the
PCM link
6.1.3
There are four counters associated with each of the
eight receive PCM links for a total of 32 Receive
counters. These counters record the following
information and are active as soon as the RX PCM
port is enabled:
the total number of cells received through the
PCM link or total number of Stuff events
received on the link (option selected in
RX Link
Control
registers)
the total number of Idle/Filler cells received
through the PCM link, , with good or bad HEC
the total number of ICP Cells with violation
received through the PCM link
the total number of cells with wrong HEC
received through the PCM link but not including
the cells where the HEC is corrected
Receive PCM I/F Counters
6.1.4
Accessing (READ) counters is a three step function.
First, the desired counter must be selected by writing
to the
Counter Select Register
. Second, the READ
command (’0x00x101’) is written to the
Counter
Transfer Command
register. This command causes
the current three byte count value to be copied from
the specified counter to the three byte-wide
Counter
Bytes
registers (note that this value is unchanged
until another counter read command is issued). And
third, the
Counter Bytes
registers are read to obtain
the three byte count value of the selected counter.
Access to the Counters
Pre-loading (WRITE) a counter is also a three step
function. First, the three byte, pre-load value, is
written to the three byte-wide
Counter Bytes
registers. Second, the identification of the counter to
be pre-loaded is written to the
Counter Select
Register
.
And
third,
(’0x00x001’) is written to the
Counter transfer
Command
register.
the
WRITE
command
Figure 17 - ATM Mixed-Mode Interface to One MT90220
(IMA Group #1)
1 UTOPIA Port
(IMA Group #2)
(3 Links in UNI Mode)
ATM
Layer
Device
3 UTOPIA Ports
(UNI)
8
Framer
1 UTOPIA Port
(3 links)
(2 links)
相關(guān)PDF資料
PDF描述
MT90220AL Octal IMA/UNI PHY Device
MT90221 Quad IMA/UNI PHY Device
MT90221AL Quad IMA/UNI PHY Device
MT9041B T1/E1 System Synchronizer
MT9041BP T1/E1 System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90220AL 制造商:Zarlink Semiconductor Inc 功能描述:I.C.
MT90220ALX01 制造商:Mitel Networks Corporation 功能描述:
MT90221 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90221AL 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device
MT90222 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device