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參數(shù)資料
| 型號(hào)： | MT90220 |
| 廠(chǎng)商： | Mitel Networks Corporation |
| 英文描述： | IC, MICREL LDO 5A ADJ VLT REG TO-2 |
| 中文描述： | 八路IMA的/單向物理層設(shè)備 |
| 文件頁(yè)數(shù)： | 22/116頁(yè) |
| 文件大小： | 306K |
| 代理商： | MT90220 |
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MT90220
14
The SCCI field is incremented by one for each
transfer command performed which includes a
change in at least one byte of the ICP cell.
2.4.8
An optional interrupt is provided at the end of an IMA
frame to simplify software implemented changes in
the Group Control and Status field. This interrupt can
be enabled on an as required and per group basis to
implement a frame counter. The
TX ICP Cell
Handler
and
TX ICP Interrupt Enable
registers are
used for the transfer ready and frame interrupt.
IMA Frame Programmable Interrupt
2.4.9
The content of the Filler cell is pre-initialized and
conforms with the IMA Specification.
Filler Cell Definition
2.4.10 TX IMA Group Start-Up
Initialize the TX IMA Group start-up as follows:
(Note: The startup procedure below is given
indicating the most important steps. A more detailed
and complete sequence can be found in the
MT90220/221 Programmer’s Manual and example
code).
Configure the TX PCM port(s) by writing to the
TX PCM Link Control
register 1 and 2.
Write the value of M, the Timing Mode and the
reference link number to the
TX Group Control
register corresponding to the IMA Group
number to be initialized.
Write the Link ID (LID is between 0-31) to
TX
Link ID
registers for each link to be used in the
IMA Group. LID should not be changed when a
group is operational. Ensure each link that is
part of an IMA group has a unique LID (note
that the MT90220 does not verify LIDs).
Write the ICP Cell Offset value to
TX ICP Cell
Offset
registers. This value depends on the
value of M. Typically, the reference link will have
a delay of 0 cells in the IMA Frame and the ICP
cell in each other link will be evenly spaced in a
multiple of M/N cells (where M is defined in the
IMA specification and N is the number of links).
The offset value for an operational group should
not be changed.
Write to the
TX Link Control
registers to put
the link(s) in IMA mode and to enable the
transfer of ATM User Cells when required.
2.4.11 TX Link Addition
The MT90220 supports software controlled link
addition to the existing IMA group. Link addition is
used to increase the available bandwidth. The
TX
PCM Link Control register 1
and
2, the TX Link ID
and
TX ICP Cell Offset
registers are initialized first
with the proper IMA Group information. The link is
assigned to a TX IMA group by writing to the lower 2
bits of the
TX Link Control
register. The bit 3, 1 and
0 of the
Test 2
register have to be written with the
proper value. The link is then configured in IMA
mode by writing to the bit 2 of the
TX Link Contro
l
register. The
TX IMA Mode
Status register is
monitored to detect when the link is reported in IMA
mode. When the link is in IMA mode, then the bit 3, 1
and 0 of the Test 2 register are reset to 0.
TX Link
control
register bit 6 determines when ATM User
cells can be sent. Note that the
Test 2
register
cannot be used as a read/modify/write register. The
values that are written and the values that are read
are independant. Note also that the bit 6 of the
Test
2
register should always be set to 1.
2.4.12 TX Link Deletion
There are two reasons to remove a link: the required
bandwidth decreases or a link becomes faulty. The
MT90220 supports link deactivation under software
control.
A link stops transmitting User cells when bit 6 of the
TX Link Control register
is set to 0. Filler and ICP
cells will still be sent on the link. The link is removed
from an IMA group by first setting the bit 2 of the
TX
Link Control register
to 1 while keeping the original
IMA group number. The IMA group number can be
changed only when the link is in UNI mode as
Figure 4 - Functional Block Diagram of the Transmitter in UNI Mode
(For Link[N] where 1
≤
N
≤
8)
ATM In
Cell_In_Control
Cell RAM
Tx Link [N] FIFO
P/S
Link [N]
Serial
Streams
Transmitter
Output Controller and
Cell Distribution
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90220AL | Octal IMA/UNI PHY Device |
| MT90221 | Quad IMA/UNI PHY Device |
| MT90221AL | Quad IMA/UNI PHY Device |
| MT9041B | T1/E1 System Synchronizer |
| MT9041BP | T1/E1 System Synchronizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90220AL | 制造商:Zarlink Semiconductor Inc 功能描述:I.C. |
| MT90220ALX01 | 制造商:Mitel Networks Corporation 功能描述: |
| MT90221 | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90221AL | 制造商:MITEL 制造商全稱(chēng):Mitel Networks Corporation 功能描述:Quad IMA/UNI PHY Device |
| MT90222 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:4/8/16 Port IMA/TC PHY Device |
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