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參數(shù)資料
| 型號： | MT58V1MV18DT-10 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 CACHE SRAM, 5 ns, PQFP100 |
| 封裝： | PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 13/34頁 |
| 文件大?。?/td> | 521K |
| 代理商： | MT58V1MV18DT-10 |
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18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_16_D.fm – Rev. D, Pub 2/03
20
2003 Micron Technology, Inc.
Figure 9:
READ/WRITE Timing
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following
A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC#, or ADV# cycle is performed.
(This note applies to whole diagram.)
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. This undefined READ will follow any WRITE cycle which is transitioned to a Read, Deselect, or Snooze.
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 5)
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
BWE#,
BWa#-BWd#
(NOTE 4)
A3
DON’T CARE
UNDEFINED
(NOTE 6)
(NOTE 3)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58V1MV18DT-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58V1MV18DT-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT58V1MV18FT-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58V1MV18FT-7.5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58V512V32D | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:16Mb SYNCBURST⑩ SRAM |
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