參數(shù)資料
型號(hào)： MT58L512Y36FT-8.5
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： SRAM
英文描述： 512K X 36 CACHE SRAM, 8.5 ns, PQFP100
封裝： PLASTIC, TQFP-100
文件頁(yè)數(shù)： 3/34頁(yè)
文件大小： 537K
代理商： MT58L512Y36FT-8.5
18Mb: 1 MEG x 18, 512K x 32/36
FLOW-THROUGH SYNCBURST SRAM
18Mb: 1 Meg x 18, 512K x 32/36, Flow-Through SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18F_16_D.fm – Rev. D, Pub. 2/03
11
2003 Micron Technology, Inc.
NOTE:
1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc#, or BWd#) and BWE# are LOW
or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables writes to DQa pins/balls and DQPa. BWb# enables writes to DQb pins/balls and DQPb. BWc# enables
writes to DQc pins/balls and DQPc. BWd# enables writes to DQd pins/balls and DQPd. DQPa and DQPb are only avail-
able on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L–H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L–H edge of CLK. Refer to WRITE timing
diagram for clarification.
Table 7:
Truth Table
Notes 1–8
OPERATION
ADDRESS
USED
CE# CE2# CE2
ZZ
ADSP# ADSC#
ADV#
WRITE# OE#
CLK
DQ
Deselect Cycle, Power-
Down
None
H
X
L
X
L
X
L–H
High-Z
Deselect Cycle, Power-
Down
None
L
X
L
X
L–H
High-Z
Deselect Cycle, Power-
Down
None
L
H
X
L
X
L–H
High-Z
Deselect Cycle, Power-
Down
None
L
X
L
H
L
X
L–H
High-Z
Deselect Cycle, Power-
Down
None
L
H
X
L
H
L
X
L–H
High-Z
SNOOZE Mode, Power-
Down
None
X
H
X
High-Z
Read Cycle, Begin Burst
External
L
H
L
X
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
X
H
L–H
High-Z
Write Cycle, Begin Burst
External
L
H
L
H
L
X
L
X
L–H
D
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
H
L
X
H
L–H
High-Z
Read Cycle, Continue Burst
Next
X
L
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
X
L
H
L
H
L–H
High-Z
Read Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
H
X
L
X
H
L
H
L–H
High-Z
Write Cycle, Continue
Burst
Next
X
L
H
L
X
L–H
D
Write Cycle, Continue
Burst
Next
H
X
L
X
H
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
L
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
L
H
L–H
High-Z
Read Cycle, Suspend Burst
Current
H
X
L
X
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
H
X
L
X
H
L–H
High-Z
Write Cycle, Suspend Burst
Current
X
L
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
L
X
H
L
X
L–H
D
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