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參數(shù)資料
| 型號： | MT58L128L36P1T-5 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 2.8 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 30/30頁 |
| 文件大?。?/td> | 481K |
| 代理商： | MT58L128L36P1T-5 |
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9
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
6R
SA0
Input
Synchronous Address Inputs: These inputs are registered and
6P
SA1
must meet the setup and hold times around the rising edge of
2A, 2B, 3P,
SA
CLK.
3R, 4P, 4R,
8P, 8R, 9P, 9R,
8P, 8R, 9P,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
5B
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
4A
5A
BWb#
individual bytes to be written and must meet the setup and hold
–
4A
BWc#
times around the rising edge of CLK. A byte write enable is LOW
–
4B
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
7A
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
7B
GW#
Input
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
6B
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
3A
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
6A
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
11H
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
3B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
8B
OE#(G#)
Input
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
9A
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge
of the first clock after an ADSP# cycle is initiated.
(continued on next page)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L128L36P1T-5 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC BGA 3.3V |
| MT58L128L36P1T-6 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36P1T-6 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36P1T-7.5 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 4ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:128K X 36 CACHE SRAM, 4 ns, PQFP100 |
| MT58L128L36P1T-7.5 IT | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC IND TEMP |
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