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參數(shù)資料
| 型號： | MT58L128L36P1T-5 |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 CACHE SRAM, 2.8 ns, PQFP100 |
| 封裝： | PLASTIC, MS-026, TQFP-100 |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 481K |
| 代理商： | MT58L128L36P1T-5 |
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7
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
85
ADSC#
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to
be registered. A READ or WRITE is performed using the new
address if CE# is LOW. ADSC# is also used to place the chip into
power-down state when CE# is HIGH.
31
MODE
Input Mode: This input selects the burst sequence. A LOW on this pin
selects “l(fā)inear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
64
ZZ
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in
the memory array is retained. When ZZ is active, all other inputs
are ignored.
(a) 58, 59,
(a) 52, 53,
DQa
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte
62, 63, 68, 69, 56–59, 62, 63
Output “b” is DQb pins. For the x32 and x36 versions, Byte “a” is DQa
72, 73
pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is
(b) 8, 9, 12,
(b) 68, 69
DQb
DQd pins. Input data must meet setup and hold times around
13, 18, 19, 22, 72–75, 78, 79
the rising edge of CLK.
23
(c) 2, 3, 6-9,
DQc
12, 13
(d) 18, 19,
DQd
22–25, 28, 29
74
51
NC/DQPa
NC/
No Connect/Parity Data I/Os: On the x32 version, these pins are
24
80
NC/DQPb
I/O
No Connect (NC). On the x18 version, Byte “a” parity is DQPa;
–1
NC/DQPc
Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is
–30
NC/DQPd
DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d”
parity is DQPd.
14, 15, 41, 65, 14, 15, 41, 65,
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
91
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27,
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
54, 61, 70, 77 54, 61, 70, 77
and Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21,
VSS
Supply Ground: GND.
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
38, 39
DNU
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1–3, 6, 7, 16,
16, 66
NC
–
No Connect: These signals are not internally connected and
25, 28–30,
may be connected to ground to improve package heat
51–53, 56, 57,
dissipation.
66, 75, 78, 79,
95, 96
42, 43
NF
–
No Function: These pins are internally connected to the die and
have the capacitance of input pins. It is allowable to leave these
pins unconnected or driven by signals. Reserved for address
expansion; pin 43 becomes an SA at 8Mb density and pin 42
becomes an SA at 16Mb density.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L128L36P1T-5 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC BGA 3.3V |
| MT58L128L36P1T-6 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36P1T-6 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36P1T-7.5 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 4ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:128K X 36 CACHE SRAM, 4 ns, PQFP100 |
| MT58L128L36P1T-7.5 IT | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC IND TEMP |
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