參數(shù)資料
型號: MT58L128L36P1T-5
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 128K X 36 CACHE SRAM, 2.8 ns, PQFP100
封裝: PLASTIC, MS-026, TQFP-100
文件頁數(shù): 15/30頁
文件大?。?/td> 481K
代理商: MT58L128L36P1T-5
22
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
READ TIMING3
(READ timing parameters are contained on the following page.)
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
GW#, BWE#,
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST READ
tOEQ
tOELZ
tKQHZ
ADV#
suspends
burst.
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A2 + 3)
A2
A3
(NOTE 1)
Deselect
cycle.
(NOTE 3)
(NOTE 4)
Burst continued with
new base address.
DON’T CARE
UNDEFINED
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to
be driven until after the following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MT58L128L36P1T-7.5 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 4ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述:128K X 36 CACHE SRAM, 4 ns, PQFP100
MT58L128L36P1T-7.5 IT 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC IND TEMP