- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296642 > MT48V8M16LFB4-8XT 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT48V8M16LFB4-8XT |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件頁(yè)數(shù)： | 43/69頁(yè) |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48V8M16LFB4-8XT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)當(dāng)前第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
48
2001 Micron Technology, Inc. All rights reserved.
Figure 35: Initialize and Load Mode Register
NOTE:
1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command.
2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE
command, RA = Row Address, BA = Bank Address
3. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur
prior to an Active command
4. Optional refresh command.
5. Although not required, to prevent bus contention it is suggested to keep DQM high during the Initialization sequence.
CKE
BA0, BA1
Load Extended
Mode Register
Load Mode
Register
tCKS
Power-up:
VDD and
CLK stable
T = 100s
tCKH
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DQML, DQMU5
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DQ
High-Z
A0-A9, A11
RA
A10
RA
ALL BANKS
CLK
tCK
LMR3
NOP
PRE
LMR3
AR
AR4
ACT
tCMS tCMH
BA0 = L,
BA1 = H
tAS tAH
tAS tAH
BA0 = L,
BA1 = L
(
)
(
)
(
)
(
)
CODE
tAS tAH
CODE
(
)
(
)
(
)
(
)
PRE
ALL BANKS
tAS tAH
(
)
(
)
(
)
(
)
T0
T1
T3
T5
T7
T9
T19
T29
DON’T CARE
BA
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
tRP
tMRD
tRP
tRFC
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
COMMAND1,2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT48LC4M32LFB5-10ES:G | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PBGA90 |
| MT48V4M32TG-8XT | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| MT48LC8M8A2TG-8EL:GIT | 8M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO54 |
| MT4JSF6464HIY-80BXX | 64M X 64 DDR DRAM MODULE, ZMA204 |
| MT4JSF6464HY-1G4XX | 64M X 64 DDR DRAM MODULE, ZMA204 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48V8M16LFF4-8 XT | 制造商:Micron Technology Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。