參數(shù)資料
型號(hào)： MT48V8M16LFB4-8XT
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝： 8 X 8 MM, LEAD FREE, VFBGA-54
文件頁數(shù)： 36/69頁
文件大?。?/td> 6213K
代理商： MT48V8M16LFB4-8XT
128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
41
2001 Micron Technology, Inc. All rights reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 14).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figure 16 and Figure 17). DQM should be used one clock prior to the
WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 24), with the data-out appearing CAS latency later. The last valid
WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank will
interrupt the WRITE on bank n when registered (Figure 22). The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is reg-
istered (Figure 31).
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent
bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 32).
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank
n will be data-in registered one clock prior to the READ to bank m (Figure 33).
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the
WRITE to bank m (Figure 34).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48V8M16LFF4-8 XT 制造商:Micron Technology Inc 功能描述:
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